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PIC18F1220/1320 Data Sheet
18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
(c) 2007 Microchip Technology Inc.
DS39605F
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS39605F-page ii
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
18/20/28-Pin High-Performance, Enhanced Flash MCUs with 10-bit A/D and nanoWatt Technology
Low-Power Features:
* Power Managed modes: - Run: CPU on, peripherals on - Idle: CPU off, peripherals on - Sleep: CPU off, peripherals off * Power Consumption modes: - PRI_RUN: 150 A, 1 MHz, 2V - PRI_IDLE: 37 A, 1 MHz, 2V - SEC_RUN: 14 A, 32 kHz, 2V - SEC_IDLE: 5.8 A, 32 kHz, 2V - RC_RUN: 110 A, 1 MHz, 2V - RC_IDLE: 52 A, 1 MHz, 2V - Sleep: 0.1 A, 1 MHz, 2V * Timer1 Oscillator: 1.1 A, 32 kHz, 2V * Watchdog Timer: 2.1 A * Two-Speed Oscillator Start-up
Peripheral Highlights:
* High current sink/source 25 mA/25 mA * Three external interrupts * Enhanced Capture/Compare/PWM (ECCP) module: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-Shutdown and Auto-Restart - Capture is 16-bit, max resolution 6.25 ns (TCY/16) - Compare is 16-bit, max resolution 100 ns (TCY) * Compatible 10-bit, up to 13-channel Analog-toDigital Converter module (A/D) with programmable acquisition time * Enhanced USART module: - Supports RS-485, RS-232 and LIN 1.2 - Auto-Wake-up on Start bit - Auto-Baud Detect
Oscillators:
* Four Crystal modes: - LP, XT, HS: up to 25 MHz - HSPLL: 4-10 MHz (16-40 MHz internal) * Two External RC modes, up to 4 MHz * Two External Clock modes, up to 40 MHz * Internal oscillator block: - 8 user-selectable frequencies: 31 kHz, 125 kHz, 250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz - 125 kHz to 8 MHz calibrated to 1% - Two modes select one or two I/O pins - OSCTUNE - Allows user to shift frequency * Secondary oscillator using Timer1 @ 32 kHz * Fail-Safe Clock Monitor - Allows for safe shutdown if peripheral clock stops
Special Microcontroller Features:
* 100,000 erase/write cycle Enhanced Flash program memory typical * 1,000,000 erase/write cycle Data EEPROM memory typical * Flash/Data EEPROM Retention: > 40 years * Self-programmable under software control * Priority levels for interrupts * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 41 ms to 131s - 2% stability over VDD and Temperature * Single-supply 5V In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * In-Circuit Debug (ICD) via two pins * Wide operating voltage range: 2.0V to 5.5V
Program Memory Device Flash (bytes) 4K 8K # Single-Word Instructions 2048 4096
Data Memory SRAM (bytes) 256 256 EEPROM (bytes) 256 256 I/O 10-bit A/D (ch) 7 7 ECCP (PWM) 1 1 EUSART Timers 8/16-bit 1/3 1/3
PIC18F1220 PIC18F1320
16 16
Y Y
(c) 2007 Microchip Technology Inc.
DS39605F-page 1
PIC18F1220/1320
Pin Diagrams
18-Pin PDIP, SOIC
RA0/AN0 RA1/AN1/LVDIN RA4/T0CKI MCLR/VPP/RA5 VSS/AVSS RA2/AN2/VREFRA3/AN3/VREF+ RB0/AN4/INT0 RB1/AN5/TX/ CK/INT1 1 2 18 17 RB3/CCP1/P1A RB2/P1B/INT2 OSC1/CLKI/RA7 OSC2/CLKO/RA6 VDD/AVDD RB7/PGD/T1OSI/ P1D/KBI3 RB6/PGC/T1OSO/ T13CKI/P1C/KBI2 RB5/PGM/KBI1 RB4/AN6/RX/ DT/KBI0
20-Pin SSOP
RA0/AN0 RA1/AN1/LVDIN RA4/T0CKI MCLR/VPP/RA5 VSS AVSS RA2/AN2/VREFRA3/AN3/VREF+ RB0/AN4/INT0 RB1/AN5/TX/ CK/INT1 1 2 3 20 19 18 RB3/CCP1/P1A RB2/P1B/INT2 OSC1/CLKI/RA7 OSC2/CLKO/RA6 VDD AVDD RB7/PGD/T1OSI/ P1D/KBI3 RB6/PGC/T1OSO/ T13CKI/P1C/KBI2 RB5/PGM/KBI1 RB4/AN6/RX/ DT/KBI0
PIC18F1X20
3 4 5 6 7 8 9
16 15 14 13 12 11 10
5 6 7 8 9 10
PIC18F1X20
4
17 16 15 14 13 12 11
RB3/CCP1/P1A 24
RB2/P1B/INT2 23
28-Pin QFN
RA4/T0CKI
RA1/AN1/LVDIN
RA0/AN0
28
27
26
25
NC
MCLR/VPP/RA5 NC VSS NC AVSS NC RA2/AN2/VREF-
22 21 20 19
1 2 3 4 5 6 7 10 11 12 13 14 8 9
NC
OSC1/CLKI/RA7 OSC2/CLKO/RA6 VDD NC AVDD RB7/PGD/T1OSI/P1D/KBI3 RB6/PGC/T1OSO/T13CKI/P1C/KBI2
PIC18F1X20
18 17 16 15
RA3/AN3/VREF+
RB1/AN5/TX/CK/INT1
RB4/AN6/RX/DT/KBI0
RB5/PGM/KBI1
RB0/AN4/INT0
NC
NC
DS39605F-page 2
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Oscillator Configurations ............................................................................................................................................................ 11 3.0 Power Managed Modes ............................................................................................................................................................. 19 4.0 Reset .......................................................................................................................................................................................... 33 5.0 Memory Organization ................................................................................................................................................................. 41 6.0 Flash Program Memory.............................................................................................................................................................. 57 7.0 Data EEPROM Memory ............................................................................................................................................................. 67 8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 71 9.0 Interrupts .................................................................................................................................................................................... 73 10.0 I/O Ports ..................................................................................................................................................................................... 87 11.0 Timer0 Module ........................................................................................................................................................................... 99 12.0 Timer1 Module ......................................................................................................................................................................... 103 13.0 Timer2 Module ......................................................................................................................................................................... 109 14.0 Timer3 Module ......................................................................................................................................................................... 111 15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 115 16.0 Enhanced Addressable Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .......................................... 131 17.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 155 18.0 Low-Voltage Detect .................................................................................................................................................................. 165 19.0 Special Features of the CPU.................................................................................................................................................... 171 20.0 Instruction Set Summary .......................................................................................................................................................... 191 21.0 Development Support............................................................................................................................................................... 233 22.0 Electrical Characteristics .......................................................................................................................................................... 237 23.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 267 24.0 Packaging Information.............................................................................................................................................................. 285 Appendix A: Revision History............................................................................................................................................................. 291 Appendix B: Device Differences ........................................................................................................................................................ 291 Appendix C: Conversion Considerations ........................................................................................................................................... 292 Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 292 Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 293 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 293 Index .................................................................................................................................................................................................. 295 The Microchip Web Site ..................................................................................................................................................................... 303 Customer Change Notification Service .............................................................................................................................................. 303 Customer Support .............................................................................................................................................................................. 303 Reader Response .............................................................................................................................................................................. 304 PIC18F1220/1320 Product Identification System .............................................................................................................................. 305
(c) 2007 Microchip Technology Inc.
DS39605F-page 3
PIC18F1220/1320
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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DS39605F-page 4
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
1.0 DEVICE OVERVIEW
This document contains device specific information for the following devices: * PIC18F1220 * PIC18F1320 Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation, or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Poweron Reset, or wake-up from Sleep mode, until the primary clock source is available. This allows for code execution during what would otherwise be the clock start-up interval and can even allow an application to perform routine background activities and return to Sleep without returning to full power operation.
This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price - with the addition of high endurance Enhanced Flash program memory. On top of these features, the PIC18F1220/1320 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications.
1.1
1.1.1
New Core Features
nanoWatt TECHNOLOGY
All of the devices in the PIC18F1220/1320 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. * Multiple Idle Modes: The controller can also run with its CPU core disabled, but the peripherals are still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. * On-the-fly Mode Switching: The power managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application's software design. * Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 A, respectively.
1.2
Other Special Features
1.1.2
MULTIPLE OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC18F1220/1320 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: * Four Crystal modes, using crystals or ceramic resonators. * Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output), or one pin (oscillator input, with the second pin reassigned as general I/O). * Two External RC Oscillator modes, with the same pin options as the External Clock modes. * An internal oscillator block, which provides an 8 MHz clock (2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of 6 user-selectable clock frequencies (from 125 kHz to 4 MHz) for a total of 8 clock frequencies.
* Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles - up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. * Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown, for disabling PWM outputs on interrupt or other select conditions and auto-restart, to reactivate outputs once the condition has cleared. * Enhanced USART: This serial communication module features automatic wake-up on Start bit and automatic baud rate detection and supports RS-232, RS-485 and LIN 1.2 protocols, making it ideally suited for use in Local Interconnect Network (LIN) bus applications. * 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 2 minutes that is stable across operating voltage and temperature.
(c) 2007 Microchip Technology Inc.
DS39605F-page 5
PIC18F1220/1320
1.3 Details on Individual Family Members
A block diagram of the PIC18F1220/1320 device architecture is provided in Figure 1-1. The pinouts for this device family are listed in Table 1-2.
Devices in the PIC18F1220/1320 family are available in 18-pin, 20-pin and 28-pin packages. A block diagram for this device family is shown in Figure 1-1. The devices are differentiated from each other only in the amount of on-chip Flash program memory (4 Kbytes for the PIC18F1220 device, 8 Kbytes for the PIC18F1320 device). These and other features are summarized in Table 1-1.
TABLE 1-1:
DEVICE FEATURES
Features PIC18F1220 DC - 40 MHz 4096 2048 256 256 15 Ports A, B 4 1 Enhanced USART 7 input channels PIC18F1320 DC - 40 MHz 8192 4096 256 256 15 Ports A, B 4 1 Enhanced USART 7 input channels
Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Data EEPROM Memory (Bytes) Interrupt Sources I/O Ports Timers Enhanced Capture/Compare/PWM Modules Serial Communications 10-bit Analog-to-Digital Module Resets (and Delays) Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Packages
POR, BOR, POR, BOR, RESET Instruction, Stack Full, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), Stack Underflow (PWRT, OST), MCLR (optional), WDT MCLR (optional), WDT Yes Yes 75 Instructions 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN Yes Yes 75 Instructions 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN
DS39605F-page 6
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 1-1: PIC18F1220/1320 BLOCK DIAGRAM
Data Bus<8>
21 Table Pointer <2> 21 21 Address Latch Program Memory (4 Kbytes) PIC18F1220 (8 Kbytes) PIC18F1320 Data Latch 16 Table Latch 8 20 inc/dec logic
8
8
8
8
Data Latch Data RAM
PORTA RA0/AN0 RA1/AN1/LVDIN
Address Latch PCLATU PCLATH PCU PCH PCL Program Counter RA2/AN2/VREF12(2) Address<12> 4 BSR 12 4 FSR0 Bank0, F FSR1 FSR2 12 RA3/AN3/VREF+ RA4/T0CKI MCLR/VPP/RA5(1) OSC2/CLKO/RA6(2) OSC2/CLKI/RA7(2)
31 Level Stack
Decode
inc/dec logic
ROM Latch
PORTB RB0/AN4/INT0
Instruction Register Instruction Decode & Control 3 8 PRODH PRODL 8 x 8 Multiply 8 OSC1(2) OSC2(2) T1OSI T1OSO Timing Generation INTRC Oscillator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Low-Voltage Programming In-Circuit Debugger Brown-out Reset Fail-Safe Clock Monitor Precision Voltage Reference BIT OP 8 WREG 8 8 ALU<8> 8 8
RB1/AN5/TX/CK/INT1 RB2/P1B/INT2 RB3/CCP1/P1A RB4/AN6/RX/DT/KBI0 RB5/PGM/KBI1 RB6/PGC/T1OSO/ T13CKI/P1C/KBI2 RB7/PGD/T1OSI/ P1D/KBI3
MCLR
(1)
VDD, VSS
Timer0
Timer1
Timer2
Timer3
A/D Converter
Enhanced CCP
Enhanced USART
Data EEPROM
Note
1: RA5 is available only when the MCLR Reset is disabled. 2: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 "Oscillator Configurations" for additional information.
(c) 2007 Microchip Technology Inc.
DS39605F-page 7
PIC18F1220/1320
TABLE 1-2:
Pin Name
PIC18F1220/1320 PINOUT I/O DESCRIPTIONS
Pin Number PDIP/ SSOP SOIC 4 4 QFN 1 I P I 16 18 21 I ST -- ST ST Pin Type Buffer Type Description
MCLR/VPP/RA5 MCLR VPP RA5 OSC1/CLKI/RA7 OSC1
Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input.
CLKI
I
RA7 OSC2/CLKO/RA6 OSC2 CLKO 15 17 20
I/O O O
Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) ST General purpose I/O pin. -- -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC, EC and INTRC modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes instruction cycle rate. General purpose I/O pin. PORTA is a bidirectional I/O port.
RA6 RA0/AN0 RA0 AN0 RA1/AN1/LVDIN RA1 AN1 LVDIN RA2/AN2/VREFRA2 AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI RA4 T0CKI RA5 RA6 RA7 Legend: TTL ST O OD = = = = 1 1 26
I/O
ST
I/O I 2 2 27 I/O I I 6 7 7 I/O I I 7 8 8 I/O I I 3 3 28 I/O I
ST Analog ST Analog Analog ST Analog Analog ST Analog Analog ST/OD ST
Digital I/O. Analog input 0. Digital I/O. Analog input 1. Low-Voltage Detect input. Digital I/O. Analog input 2. A/D reference voltage (low) input. Digital I/O. Analog input 3. A/D reference voltage (high) input. Digital I/O. Open-drain when configured as output. Timer0 external clock input. See the MCLR/VPP/RA5 pin. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin.
TTL compatible input Schmitt Trigger input with CMOS levels Output Open-drain (no P diode to VDD)
CMOS = CMOS compatible input or output I = Input P = Power
DS39605F-page 8
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 1-2:
Pin Name
PIC18F1220/1320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP/ SSOP SOIC QFN Pin Type Buffer Type Description
PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN4/INT0 RB0 AN4 INT0 RB1/AN5/TX/CK/INT1 RB1 AN5 TX CK INT1 RB2/P1B/INT2 RB2 P1B INT2 RB3/CCP1/P1A RB3 CCP1 P1A RB4/AN6/RX/DT/KBI0 RB4 AN6 RX DT KBI0 RB5/PGM/KBI1 RB5 PGM KBI1 RB6/PGC/T1OSO/ T13CKI/P1C/KBI2 RB6 PGC T1OSO T13CKI P1C KBI2 RB7/PGD/T1OSI/ P1D/KBI3 RB7 PGD T1OSI P1D KBI3 VSS VDD NC Legend: TTL ST O OD = = = = 8 9 9 I/O I I 9 10 10 I/O I O I/O I 17 19 23 I/O O I 18 20 24 I/O I/O O 10 11 12 I/O I I I/O I 11 12 13 I/O I/O I 12 13 15 I/O I/O O I O I 13 14 16 I/O I/O I O I 5 14 -- 5, 6 -- 3, 5 18 P P -- 15, 16 17, 19 TTL ST CMOS -- TTL -- -- -- Digital I/O. In-Circuit Debugger and ICSP programming data pin. Timer1 oscillator input. Enhanced CCP1/PWM output. Interrupt-on-change pin. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. No connect. CMOS = CMOS compatible input or output I = Input P = Power TTL ST -- ST -- TTL Digital I/O. In-Circuit Debugger and ICSP programming clock pin. Timer1 oscillator output. Timer1/Timer3 external clock output. Enhanced CCP1/PWM output. Interrupt-on-change pin. TTL ST TTL Digital I/O. Low-Voltage ICSP Programming enable pin. Interrupt-on-change pin. TTL Analog ST ST TTL Digital I/O. Analog input 6. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). Interrupt-on-change pin. TTL ST -- Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output. Enhanced CCP1/PWM output. TTL -- ST Digital I/O. Enhanced CCP1/PWM output. External interrupt 2. TTL Analog -- ST ST Digital I/O. Analog input 5. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). External interrupt 1. TTL Analog ST Digital I/O. Analog input 4. External interrupt 0.
TTL compatible input Schmitt Trigger input with CMOS levels Output Open-drain (no P diode to VDD)
(c) 2007 Microchip Technology Inc.
DS39605F-page 9
PIC18F1220/1320
NOTES:
DS39605F-page 10
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
2.0
2.1
OSCILLATOR CONFIGURATIONS
Oscillator Types
FIGURE 2-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION)
OSC1 To Internal Logic Sleep
The PIC18F1220 and PIC18F1320 devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. 5. 6. 7. 8. LP XT HS HSPLL RC RCIO INTIO1 INTIO2 Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL enabled External Resistor/Capacitor with FOSC/4 output on RA6 External Resistor/Capacitor with I/O on RA6 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 Internal Oscillator with I/O on RA6 and RA7 External Clock with FOSC/4 output External Clock with I/O on RA6
C1(1)
XTAL
RS(2) C2(1) OSC2
RF(3)
PIC18FXXXX
Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen.
TABLE 2-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS
9. EC 10. ECIO
Typical Capacitor Values Used: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1 56 pF 47 pF 33 pF 27 pF 22 pF OSC2 56 pF 47 pF 33 pF 27 pF 22 pF
2.2
Crystal Oscillator/Ceramic Resonators
In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer's specifications.
HS
Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table 2-2 for additional information. Resonators Used: 455 kHz 2.0 MHz 16.0 MHz 4.0 MHz 8.0 MHz
(c) 2007 Microchip Technology Inc.
DS39605F-page 11
PIC18F1220/1320
TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Crystal Freq 32 kHz 200 kHz XT HS 1 MHz 4 MHz 4 MHz 8 MHz 20 MHz Typical Capacitor Values Tested: C1 LP 33 pF 15 pF 33 pF 27 pF 27 pF 22 pF 15 pF C2 33 pF 15 pF 33 pF 27 pF 27 pF 22 pF 15 pF
Clock from Ext. System Open OSC1
An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2.
FIGURE 2-2:
Osc Type
EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION)
PIC18FXXXX
OSC2 (HS Mode)
2.3
HSPLL
Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz
A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency crystal oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals. The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLL is enabled only when the oscillator configuration bits are programmed for HSPLL mode. If programmed for any other mode, the PLL is not enabled.
FIGURE 2-3:
Note 1: Higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: RS may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
/4 OSC2 OSC1
PLL BLOCK DIAGRAM
HS Oscillator Enable PLL Enable (from Configuration Register 1H)
Crystal FIN Osc FOUT
Phase Comparator
Loop Filter
VCO MUX
SYSCLK
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PIC18F1220/1320
2.4 External Clock Input 2.5 RC Oscillator
The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset, or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes, or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode. For timing insensitive applications, the "RC" and "RCIO" device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation, due to tolerance of external R and C components used. Figure 2-6 shows how the R/C combination is connected. In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes, or to synchronize other logic.
FIGURE 2-4:
EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION)
OSC1/CLKI
Clock from Ext. System FOSC/4
PIC18FXXXX
OSC2/CLKO
FIGURE 2-6:
VDD
RC OSCILLATOR MODE
The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows the pin connections for the ECIO Oscillator mode.
REXT OSC1 CEXT VSS FOSC/4 OSC2/CLKO Internal Clock
PIC18FXXXX
FIGURE 2-5:
EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)
OSC1/CLKI
Recommended values: 3 k REXT 100 k CEXT > 20 pF
Clock from Ext. System RA6
PIC18FXXXX
I/O (OSC2)
The RCIO Oscillator mode (Figure 2-7) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6).
FIGURE 2-7:
VDD REXT
RCIO OSCILLATOR MODE
OSC1 CEXT VSS RA6 I/O (OSC2)
Internal Clock
PIC18FXXXX
Recommended values: 3 k REXT 100 k CEXT > 20 pF
(c) 2007 Microchip Technology Inc.
DS39605F-page 13
PIC18F1220/1320
2.6 Internal Oscillator Block
2.6.2 INTRC OUTPUT FREQUENCY
The PIC18F1220/1320 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system's clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the system clock. It also drives a postscaler, which can provide a range of clock frequencies from 125 kHz to 4 MHz. The INTOSC output is enabled when a system clock frequency from 125 kHz to 8 MHz is selected. The other clock source is the internal RC oscillator (INTRC), which provides a 31 kHz output. The INTRC oscillator is enabled by selecting the internal oscillator block as the system clock source, or when any of the following are enabled: * * * * Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz (see Table 22-6). This changes the frequency of the INTRC source from its nominal 31.25 kHz. Peripherals and features that depend on the INTRC source will be affected by this shift in frequency. Once set during factory calibration, the INTRC frequency will remain within 2% as temperature and VDD change across their full specified operating ranges.
2.6.3
OSCTUNE REGISTER
The internal oscillator's output has been calibrated at the factory, but can be adjusted in the user's application. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range. When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 s = 256 s). The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. Operation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency.
These features are discussed in greater detail in Section 19.0 "Special Features of the CPU". The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (Register 2-2).
2.6.1
INTIO MODES
Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: * In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. * In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.
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PIC18F1220/1320
REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 -- bit 7 bit 7-6 bit 5-0 Unimplemented: Read as `0' TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency * * * * 000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 * * * * 100000 = Minimum frequency Legend: R = Readable bit -n = Value at POR U-0 -- R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
2.7
Clock Sources and Oscillator Switching
Like previous PIC18 devices, the PIC18F1220/1320 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F1220/ 1320 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various power managed operating modes. Essentially, there are three clock sources for these devices: * Primary oscillators * Secondary oscillators * Internal oscillator block The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined on POR by the contents of Configuration Register 1H. The details of these modes are covered earlier in this chapter. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power managed mode.
PIC18F1220/1320 devices offer only the Timer1 oscillator as a secondary oscillator. This oscillator, in all power managed modes, is often the time base for functions such as a real-time clock. Most often, a 32.768 kHz watch crystal is connected between the RB6/T1OSO and RB7/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground. These pins are also used during ICSP operations. The Timer1 oscillator is discussed in greater detail in Section 12.2 "Timer1 Oscillator". In addition to being a primary clock source, the internal oscillator block is available as a power managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F1220/1320 devices are shown in Figure 2-8. See Section 12.0 "Timer1 Module" for further details of the Timer1 oscillator. See Section 19.1 "Configuration Bits" for configuration register details.
(c) 2007 Microchip Technology Inc.
DS39605F-page 15
PIC18F1220/1320
2.7.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several aspects of the system clock's operation, both in full power operation and in power managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source that is used when the device is operating in power managed modes. The available clock sources are the primary clock (defined in Configuration Register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock selection has no effect until a SLEEP instruction is executed and the device enters a power managed mode of operation. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source, the INTOSC source (8 MHz), or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz). If the internal oscillator block is supplying the system clock, changing the states of these bits will have an immediate change on the internal oscillator's output. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the system clock. The OSTS indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the system clock in Primary Clock modes. The IOFS bit indicates when the internal oscillator block has stabilized and is providing the system clock in RC Clock modes or during Two-Speed Start-ups. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the system clock in Secondary Clock modes. In power managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the system clock, or the internal oscillator block has just started and is not yet stable. The IDLEN bit controls the selective shutdown of the controller's CPU in power managed modes. The uses of these bits are discussed in more detail in Section 3.0 "Power Managed Modes". Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts.
FIGURE 2-8:
PIC18F1220/1320 CLOCK DIAGRAM
PIC18F1220/1320
Primary Oscillator CONFIG1H <3:0> 4 x PLL HSPLL LP, XT, HS, RC, EC MUX Secondary Oscillator T1OSC Clock Source Option for Other Modules OSCCON<6:4> 8 4 MHz Internal Oscillator Block 8 MHz (INTOSC) 110 2 MHz Postscaler 101 100 500 kHz 250 kHz 125 kHz 31 kHz 011 010 001 000 WDT, FSCM MUX 1 MHz IDLEN 111 Internal Oscillator CPU Peripherals Clock Control
OSCCON<1:0>
OSC2 Sleep OSC1 T1OSO T1OSCEN Enable Oscillator OSCCON<6:4>
T1OSI
INTRC Source
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(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 2-2: OSCCON REGISTER
R/W-0 IDLEN bit 7 bit 7 IDLEN: Idle Enable bits 1 = Idle mode enabled; CPU core is not clocked in power managed modes 0 = Run mode enabled; CPU core is clocked in Run modes, but not Sleep mode IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (8 MHz source drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (INTRC source drives clock directly) OSTS: Oscillator Start-up Time-out Status bit 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block (RC modes) 01 = Timer1 oscillator (Secondary modes) 00 = Primary oscillator (Sleep and PRI_IDLE modes) Note 1: Depends on state of the IESO bit in Configuration Register 1H. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IRCF2 R/W-0 IRCF1 R/W-0 IRCF0 R(1) OSTS R-0 IOFS R/W-0 SCS1 R/W-0 SCS0 bit 0
bit 6-4
bit 3
bit 2
bit 1-0
(c) 2007 Microchip Technology Inc.
DS39605F-page 17
PIC18F1220/1320
2.7.2 OSCILLATOR TRANSITIONS
The PIC18F1220/1320 devices contain circuitry to prevent clocking "glitches" when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Clock transitions are discussed in greater detail in Section 3.1.2 "Entering Power Managed Modes". If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a realtime clock. Other features may be operating that do not require a system clock source (i.e., INTn pins, A/D conversions and others).
2.8
Effects of Power Managed Modes on the Various Clock Sources
2.9
Power-up Delays
When the device executes a SLEEP instruction, the system is switched to one of the power managed modes, depending on the state of the IDLEN and SCS1:SCS0 bits of the OSCCON register. See Section 3.0 "Power Managed Modes" for details. When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In Secondary Clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the system clock. The Timer1 oscillator may also run in all power managed modes if required to clock Timer1 or Timer3. In Internal Oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the system clock source. The INTRC output can be used directly to provide the system clock and may be enabled to support various special features, regardless of the power managed mode (see Section 19.2 "Watchdog Timer (WDT)" through Section 19.4 "Fail-Safe Clock Monitor"). The INTOSC output at 8 MHz may be used directly to clock the system, or may be divided down first. The INTOSC output is disabled if the system clock is provided directly from the INTRC output.
Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Sections 4.1 through 4.5. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 22-8) if enabled in Configuration Register 2L. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of 5 to 10 s following POR while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source.
TABLE 2-3:
RC, INTIO1 RCIO, INTIO2 ECIO EC LP, XT and HS Note:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin Floating, external resistor should pull high Floating, external resistor should pull high Floating, pulled by external clock Floating, pulled by external clock Feedback inverter disabled at quiescent voltage level OSC2 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level
Oscillator Mode
See Table 4-1 in Section 4.0 "Reset" for time-outs due to Sleep and MCLR Reset.
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PIC18F1220/1320
3.0 POWER MANAGED MODES
The PIC18F1220/1320 devices offer a total of six operating modes for more efficient power management (see Table 3-1). These provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery powered devices). There are three categories of power managed modes: * Sleep mode * Idle modes * Run modes These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or INTOSC multiplexer); the Sleep mode does not use a clock source. The clock switching feature offered in other PIC18 devices (i.e., using the Timer1 oscillator in place of the primary oscillator) and the Sleep mode offered by all PIC(R) devices (where all system clocks are stopped) are both offered in the PIC18F1220/1320 devices (SEC_RUN and Sleep modes, respectively). However, additional power managed modes are available that allow the user greater flexibility in determining what portions of the device are operating. The power managed modes are event driven; that is, some specific event must occur for the device to enter or (more particularly) exit these operating modes. For PIC18F1220/1320 devices, the power managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a Reset or a WDT time-out (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source). In addition, power managed Run modes may also exit to Sleep mode, or their corresponding Idle mode.
3.1
Selecting Power Managed Modes
Selecting a power managed mode requires deciding if the CPU is to be clocked or not and selecting a clock source. The IDLEN bit controls CPU clocking, while the SCS1:SCS0 bits select a clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1.
3.1.1
CLOCK SOURCES
The clock source is selected by setting the SCS bits of the OSCCON register (Register 2-2). Three clock sources are available for use in power managed Idle modes: the primary clock (as configured in Configuration Register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The secondary and internal oscillator block sources are available for the power managed modes (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source).
TABLE 3-1:
Mode Sleep PRI_RUN SEC_RUN RC_RUN PRI_IDLE SEC_IDLE RC_IDLE Note 1:
POWER MANAGED MODES
OSCCON Bits IDLEN <7> 0 0 0 0 1 1 1 SCS1:SCS0 <1:0> 00 00 01 1x 00 01 1x Module Clocking Available Clock and Oscillator Source CPU Off Clocked Clocked Clocked Off Off Off Peripherals Off Clocked Clocked Clocked Clocked Clocked Clocked None - All clocks are disabled Primary - LP, XT, HS, HSPLL, RC, EC, INTRC(1) This is the normal full power execution mode. Secondary - Timer1 Oscillator Internal Oscillator Block(1) Primary - LP, XT, HS, HSPLL, RC, EC Secondary - Timer1 Oscillator Internal Oscillator Block(1)
Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
(c) 2007 Microchip Technology Inc.
DS39605F-page 19
PIC18F1220/1320
3.1.2 ENTERING POWER MANAGED MODES
In general, entry, exit and switching between power managed clock sources requires clock source switching. In each case, the sequence of events is the same. Any change in the power managed mode begins with loading the OSCCON register and executing a SLEEP instruction. The SCS1:SCS0 bits select one of three power managed clock sources; the primary clock (as defined in Configuration Register 1H), the secondary clock (the Timer1 oscillator) and the internal oscillator block (used in RC modes). Modifying the SCS bits will have no effect until a SLEEP instruction is executed. Entry to the power managed mode is triggered by the execution of a SLEEP instruction. Figure 3-5 shows how the system is clocked while switching from the primary clock to the Timer1 oscillator. When the SLEEP instruction is executed, clocks to the device are stopped at the beginning of the next instruction cycle. Eight clock cycles from the new clock source are counted to synchronize with the new clock source. After eight clock pulses from the new clock source are counted, clocks from the new clock source resume clocking the system. The actual length of the pause is between eight and nine clock periods from the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Three bits indicate the current clock source: OSTS and IOFS in the OSCCON register and T1RUN in the T1CON register. Only one of these bits will be set while in a power managed mode. When the OSTS bit is set, the primary clock is providing the system clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source and is providing the system clock. When the T1RUN bit is set, the Timer1 oscillator is providing the system clock. If none of these bits are set, then either the INTRC clock source is clocking the system, or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source in Configuration Register 1H, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering an RC power managed mode (same frequency) would clear the OSTS bit. Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode; executing a SLEEP instruction is simply a trigger to place the controller into a power managed mode selected by the OSCCON register, one of which is Sleep mode.
3.1.3
MULTIPLE SLEEP COMMANDS
The power managed mode that is invoked with the SLEEP instruction is determined by the settings of the IDLEN and SCS bits at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power managed mode specified by these same bits at that time. If the bits have changed, the device will enter the new power managed mode specified by the new bit settings.
3.1.4
COMPARISONS BETWEEN RUN AND IDLE MODES
Clock source selection for the Run modes is identical to the corresponding Idle modes. When a SLEEP instruction is executed, the SCS bits in the OSCCON register are used to switch to a different clock source. As a result, if there is a change of clock source at the time a SLEEP instruction is executed, a clock switch will occur. In Idle modes, the CPU is not clocked and is not running. In Run modes, the CPU is clocked and executing code. This difference modifies the operation of the WDT when it times out. In Idle modes, a WDT time-out results in a wake from power managed modes. In Run modes, a WDT time-out results in a WDT Reset (see Table 3-2). During a wake-up from an Idle mode, the CPU starts executing code by entering the corresponding Run mode until the primary clock becomes ready. When the primary clock becomes ready, the clock source is automatically switched to the primary clock. The IDLEN and SCS bits are unchanged during and after the wake-up. Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode).
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PIC18F1220/1320
TABLE 3-2:
Power Managed Mode Sleep
COMPARISON BETWEEN POWER MANAGED MODES
CPU is Clocked by ... WDT Time-out causes a ... Peripherals are Clocked by ... Not clocked Clock during Wake-up (while primary becomes ready) None or INTOSC multiplexer if Two-Speed Start-up or Fail-Safe Clock Monitor are enabled
Not clocked (not running) Wake-up
Any Idle mode
Not clocked (not running) Wake-up
Primary, Secondary or Unchanged from Idle mode INTOSC multiplexer (CPU operates as in corresponding Run mode) Primary or secondary clocks or INTOSC multiplexer Unchanged from Run mode
Any Run mode
Primary or secondary clocks or INTOSC multiplexer
Reset
3.2
Sleep Mode
The power managed Sleep mode in the PIC18F1220/ 1320 devices is identical to that offered in all other PIC microcontrollers. It is entered by clearing the IDLEN and SCS1:SCS0 bits (this is the Reset state) and executing the SLEEP instruction. This shuts down the primary oscillator and the OSTS bit is cleared (see Figure 3-1). When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the system will not be clocked until the primary clock source becomes ready (see Figure 3-2), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 19.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the system clocks. The IDLEN and SCS bits are not affected by the wake-up.
If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed approximately 10 s while it becomes ready to execute code. When the CPU begins executing code, it is clocked by the same clock source as was selected in the power managed mode (i.e., when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals until the primary clock source becomes ready - this is essentially RC_RUN mode). This continues until the primary clock source becomes ready. When the primary clock becomes ready, the OSTS bit is set and the system clock source is switched to the primary clock (see Figure 3-4). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to full power operation.
3.3
Idle Modes
The IDLEN bit allows the microcontroller's CPU to be selectively shut down while the peripherals continue to operate. Clearing IDLEN allows the CPU to be clocked. Setting IDLEN disables clocks to the CPU, effectively stopping program execution (see Register 2-2). The peripherals continue to be clocked regardless of the setting of the IDLEN bit. There is one exception to how the IDLEN bit functions. When all the low-power OSCCON bits are cleared (IDLEN:SCS1:SCS0 = 000), the device enters Sleep mode upon the execution of the SLEEP instruction. This is both the Reset state of the OSCCON register and the setting that selects Sleep mode. This maintains compatibility with other PIC devices that do not offer power managed modes.
(c) 2007 Microchip Technology Inc.
DS39605F-page 21
PIC18F1220/1320
FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2
FIGURE 3-2:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 PLL Clock Output CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 PC + 6 PC + 8 TOST(1) TPLL(1)
Wake Event
OSTS bit Set
Note 1:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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PIC18F1220/1320
3.3.1 PRI_IDLE MODE
This mode is unique among the three Low-Power Idle modes, in that it does not disable the primary system clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to "warm up" or transition from another oscillator. PRI_IDLE mode is entered by setting the IDLEN bit, clearing the SCS bits and executing a SLEEP instruction. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified in Configuration Register 1H. The OSTS bit remains set in PRI_IDLE mode (see Figure 3-3). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately 10 s is required between the wake event and code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-4).
FIGURE 3-3:
TRANSITION TIMING TO PRI_IDLE MODE
Q1 Q2 Q3 Q4 Q1
OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2
FIGURE 3-4:
TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
Q1 Q2 Q3 Q4
OSC1 CPU Start-up Delay CPU Clock Peripheral Clock Program Counter PC PC + 2
Wake Event
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3.3.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered by setting the Idle bit, modifying bits, SCS1:SCS0 = 01 and executing a SLEEP instruction. When the clock source is switched (see Figure 3-5) to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After a 10 s delay following the wake event, the CPU begins executing code, being clocked by the Timer1 oscillator. The microcontroller operates in SEC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The Timer1 oscillator continues to run.
FIGURE 3-5:
TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
Q1 Q2 Q3 Q4 Q1 T1OSI OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 1 2 3 4 5 6 Clock Transition 7 8
FIGURE 3-6:
TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
T1OSI OSC1 TOST(1) PLL Clock Output CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event PC + 2 OSTS bit Set PC + 4 PC + 6 TPLL(1) 1 2 3456 Clock Transition 7 8
Note 1:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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3.3.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. This mode is entered by setting the IDLEN bit, setting SCS1 (SCS0 is ignored) and executing a SLEEP instruction. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer (see Figure 3-7), the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to a non-zero value (thus, enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable, in about 1 ms. Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a 10 s delay following the wake event, the CPU begins executing code, being clocked by the INTOSC multiplexer. The microcontroller operates in RC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wakeup. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-7:
TIMING TRANSITION TO RC_IDLE MODE
Q1 Q2 Q3 Q4 Q1 INTRC OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 1 2 3 4 5 6 7 8
Clock Transition
FIGURE 3-8:
TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC Multiplexer OSC1 TOST(1) PLL Clock Output TPLL(1) 1 2 3456 Clock Transition 7 8
CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event PC + 2 OSTS bit Set PC + 4 PC + 6
Note 1:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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3.4 Run Modes
If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits. While these operating modes may not afford the power conservation of Idle or Sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source. RC_RUN mode also offers the possibility of executing code at a frequency greater than the primary clock. Wake-up from a power managed Run mode can be triggered by an interrupt, or any Reset, to return to full power operation. As the CPU is executing code in Run modes, several additional exits from Run modes are possible. They include exit to Sleep mode, exit to a corresponding Idle mode and exit by executing a RESET instruction. While the device is in any of the power managed Run modes, a WDT time-out will result in a WDT Reset. SEC_RUN mode is entered by clearing the IDLEN bit, setting SCS1:SCS0 = 01 and executing a SLEEP instruction. The system clock source is switched to the Timer1 oscillator (see Figure 3-9), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, system clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result.
3.4.1
PRI_RUN MODE
The PRI_RUN mode is the normal full power execution mode. If the SLEEP instruction is never executed, the microcontroller operates in this mode (a SLEEP instruction is executed to enter all other power managed modes). All other power managed modes exit to PRI_RUN mode when an interrupt or WDT time-out occur. There is no entry to PRI_RUN mode. The OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1 "Oscillator Control Register").
When a wake event occurs, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The Timer1 oscillator continues to run. Firmware can force an exit from SEC_RUN mode. By clearing the T1OSCEN bit (T1CON<3>), an exit from SEC_RUN back to normal full power operation is triggered. The Timer1 oscillator will continue to run and provide the system clock, even though the T1OSCEN bit is cleared. The primary clock is started. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up.
3.4.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source.
FIGURE 3-9:
TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Q2 1 2 3 4 5 6 Clock Transition 7 8 Q3 Q4 Q1 Q2 Q3
Q1 Q2 Q3 Q4 Q1 T1OSI OSC1 CPU Clock Peripheral Clock Program Counter
PC
PC + 2
PC + 2
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3.4.3 RC_RUN MODE
Note: In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing sensitive, or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block (either of the INTIO1 or INTIO2 oscillators), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. This mode is entered by clearing the IDLEN bit, setting SCS1 (SCS0 is ignored) and executing a SLEEP instruction. The IRCF bits may select the clock frequency before the SLEEP instruction is executed. When the clock source is switched to the INTOSC multiplexer (see Figure 3-10), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the system clock speed. Executing a SLEEP instruction is not required to select a new clock frequency from the INTOSC multiplexer. Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated.
If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the system clocks. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the system continue while the INTOSC source stabilizes, in approximately 1 ms. If the IRCF bits were previously at a non-zero value before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. When a wake event occurs, the system continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-10:
TIMING TRANSITION TO RC_RUN MODE
Q1 1 2 3 4 5 6 7 8 Q2 Q3 Q4 Q1 Q2 Q3
Q4 Q1 Q2 Q3 Q4 INTRC OSC1 CPU Clock Peripheral Clock Program Counter PC
Clock Transition
PC + 2
PC + 4
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3.4.4 EXIT TO IDLE MODE
3.5
Wake from Power Managed Modes
An exit from a power managed Run mode to its corresponding Idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS or T1RUN). While the CPU is halted, the peripherals continue to be clocked from the previously selected clock source.
An exit from any of the power managed modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power managed modes. The clocking subsystem actions are discussed in each of the power managed modes (see Sections 3.2 through 3.4). Note: If application code is timing sensitive, it should wait for the OSTS bit to become set before continuing. Use the interval during the low-power exit sequence (before OSTS is set) to perform timing insensitive "housekeeping" tasks.
3.4.5
EXIT TO SLEEP MODE
An exit from a power managed Run mode to Sleep mode is executed by clearing the IDLEN and SCS1:SCS0 bits and executing a SLEEP instruction. The code is no different than the method used to invoke Sleep mode from the normal operating (full power) mode. The primary clock and internal oscillator block are disabled. The INTRC will continue to operate if the WDT is enabled. The Timer1 oscillator will continue to run, if enabled in the T1CON register (Register 12-1). All clock source status bits are cleared (OSTS, IOFS and T1RUN).
Device behavior during Low-Power mode exits is summarized in Table 3-3.
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the device to exit a power managed mode and resume full power operation. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Low-Power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 "Interrupts").
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TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES)
Primary System Clock Power Managed Mode Exit Delay Clock Ready Status Bit (OSCCON) OSTS 5-10 s(5) -- IOFS OST OST + 2 ms 5-10 s(5) 1 ms
(4)
Clock in Power Managed Mode
Activity during Wake-up from Power Managed Mode Exit by Interrupt CPU and peripherals clocked by primary clock and executing instructions. CPU and peripherals clocked by selected power managed mode clock and executing instructions until primary clock source becomes ready. Exit by Reset Not clocked or Two-Speed Start-up (if enabled)(3).
LP, XT, HS Primary System HSPLL Clock EC, RC, INTRC(1) (PRI_IDLE mode) INTOSC(2) LP, XT, HS T1OSC or INTRC(1) HSPLL EC, RC, INTRC(1) INTOSC
(2)
OSTS -- IOFS OSTS -- IOFS OSTS -- IOFS
LP, XT, HS INTOSC(2) HSPLL EC, RC, INTRC(1) INTOSC
(2)
OST OST + 2 ms 5-10 s(5) None OST OST + 2 ms 5-10 s(5) 1 ms(4)
LP, XT, HS Sleep mode HSPLL EC, RC, INTRC(1) INTOSC(2) Note 1: 2: 3: 4: 5:
Not clocked or Two-Speed Start-up (if enabled) until primary clock source becomes ready(3).
In this instance, refers specifically to the INTRC clock source. Includes both the INTOSC 8 MHz source and postscaler derived frequencies. Two-Speed Start-up is covered in greater detail in Section 19.3 "Two-Speed Start-up". Execution continues during the INTOSC stabilization period. Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other required delays (see Section 3.3 "Idle Modes").
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PIC18F1220/1320
3.5.2 EXIT BY RESET 3.5.4
Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration Register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 19.3 "Two-Speed Start-up") or Fail-Safe Clock Monitor (see Section 19.4 "Fail-Safe Clock Monitor") are enabled in Configuration Register 1H, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Since the OSCCON register is cleared following all Resets, the INTRC clock source is selected. A higher speed clock may be selected by modifying the IRCF bits in the OSCCON register. Execution is clocked by the internal oscillator block until either the primary clock becomes ready, or a power managed mode is entered before the primary clock becomes ready; the primary clock is then shut down.
EXIT WITHOUT AN OSCILLATOR START-UP DELAY
Certain exits from power managed modes do not invoke the OST at all. These are: * PRI_IDLE mode, where the primary clock source is not stopped; or * the primary clock source is not any of LP, XT, HS or HSPLL modes. In these cases, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay (approximately 10 s) following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.
3.6
INTOSC Frequency Drift
3.5.3
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions, depending on which power managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in a wake from the power managed mode (see Sections 3.2 through 3.4). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 19.2 "Watchdog Timer (WDT)"). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the system clock source.
The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz (see Table 22-6). However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register (Register 2-1). This has the side effect that the INTRC clock source frequency is also affected. However, the features that use the INTRC source often do not require an exact frequency. These features include the Fail-Safe Clock Monitor, the Watchdog Timer and the RC_RUN/ RC_IDLE modes when the INTRC clock source is selected. Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made and in some cases, how large a change is needed. Three examples follow but other techniques may be used.
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3.6.1 EXAMPLE - EUSART 3.6.3
An adjustment may be indicated when the EUSART begins to generate framing errors, or receives data with errors while in Asynchronous mode. Framing errors indicate that the system clock frequency is too high - try decrementing the value in the OSCTUNE register to reduce the system clock frequency. Errors in data may suggest that the system clock speed is too low - increment OSCTUNE.
EXAMPLE - CCP IN CAPTURE MODE
3.6.2
EXAMPLE - TIMERS
This technique compares system clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast - decrement OSCTUNE.
A CCP module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast - decrement OSCTUNE. If the measured time is much less than the calculated time, the internal oscillator block is running too slow - increment OSCTUNE.
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NOTES:
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4.0 RESET
The PIC18F1220/1320 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register (Register 4-1), RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-2. These bits are used in software to determine the nature of the Reset. See Table 4-3 for a full description of the Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. The MCLR input provided by the MCLR pin can be disabled with the MCLRE bit in Configuration Register 3H (CONFIG3H<7>).
Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a "Reset state", depending on the type of Reset that occurred.
FIGURE 4-1:
RESET Instruction Stack Pointer
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD Rise Detect VDD Brown-out Reset BOR OST/PWRT OST OSC1 32 s INTRC(1) 1024 Cycles R Q 10-bit Ripple Counter Chip_Reset S POR Pulse
PWRT
65.5 ms
11-bit Ripple Counter
Enable PWRT Enable OST(2) Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 4-1 for time-out situations.
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4.1 Power-on Reset (POR) 4.3 Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin through a resistor (1k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 33). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most low-power modes.
4.4
PLL Lock Time-out
FIGURE 4-2:
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the Oscillator Start-up Time-out.
VDD D
4.5
R1 MCLR C
Brown-out Reset (BOR)
R
PIC18FXXXX
Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
A configuration bit, BOR, can disable (if clear/ programmed), or enable (if set) the Brown-out Reset circuitry. If VDD falls below VBOR (parameter D005) for greater than TBOR (parameter 35), the brown-out situation will reset the chip. A Reset may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT (parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. Enabling BOR Reset does not automatically enable the PWRT.
4.6
Time-out Sequence
4.2
Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC18F1220/1320 is an 11-bit counter, which uses the INTRC source as the clock input. This yields a count of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation. See DC parameter 33 for details. The PWRT is enabled by clearing configuration bit, PWRTEN.
On power-up, the time-out sequence is as follows: First, after the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel. Table 4-2 shows the Reset conditions for some Special Function Registers, while Table 4-3 shows the Reset conditions for all the registers.
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TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out PWRTEN = 0 66 ms
(1)
Oscillator Configuration HSPLL HS, XT, LP EC, ECIO RC, RCIO INTIO1, INTIO2
PWRTEN = 1
(2)
Exit from Low-Power Mode 1024 TOSC + 2 ms(2) 1024 TOSC 5-10 s(3) 5-10 s(3) 5-10 s(3)
+ 1024 TOSC + 2 ms 66 ms
(1)
1024 TOSC + 2 ms(2) 1024 TOSC 5-10 s 5-10 s
(3)
66 ms(1) + 1024 TOSC 66 ms(1) 66 ms
(1)
5-10 s(3)
(3)
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the 4x PLL to lock. 3: The program memory bias start-up time is always invoked on POR, wake-up from Sleep, or on any exit from power managed mode that disables the CPU and instruction execution.
REGISTER 4-1:
RCON REGISTER BITS AND POSITIONS
R/W-0 IPEN bit 7 Note: Refer to Section 5.14 "RCON Register" for bit definitions. U-0 -- U-0 -- R/W-1 RI R/W-1 TO R/W-1 PD R/W-1 POR R/W-1 BOR bit 0
TABLE 4-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER
Program Counter 0000h 0000h 0000h 0000h 0000h 0000h RCON Register 0--1 1100 0--0 uuuu 0--1 11u0--u 1uuu 0--u 10uu 0--u 0uuu RI 1 0 1 u u u TO 1 u 1 1 1 0 PD 1 u 1 u 0 u POR 0 u u u u u BOR 0 u 0 u u u STKFUL 0 u u u u u u 0000h 0--u uuuu u u u u u 1 u 0000h PC + 2 PC + 2 u--u uuuu u--u 00uu u--u u0uu u u u u 0 u u 0 0 u u u u u u u u u STKUNF 0 u u u u u u u 1 1 u u
Condition Power-on Reset RESET Instruction Brown-out MCLR during Power Managed Run modes MCLR during Power Managed Idle modes and Sleep WDT Time-out during Full Power or Power Managed Run MCLR during Full Power Execution Stack Full Reset (STVR = 1) Stack Underflow Reset (STVR = 1) Stack Underflow Error (not an actual Reset, STVR = 0) WDT Time-out during Power Managed Idle or Sleep Interrupt Exit from Power Managed modes
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0' Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h).
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 Power-on Reset, Brown-out Reset ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx MCLR Resets WDT Reset RESET Instruction Stack Resets ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu Wake-up via WDT or Interrupt ---0 uuuu(3) uuuu uuuu(3) uuuu uuuu(3) uu-u uuuu(3) ---u uuuu uuuu uuuu PC + 2(2) --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(1) uuuu -u-u(1) uu-u u-uu(1) N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu
TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 5 of PORTA is enabled if MCLR is disabled.
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TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 Power-on Reset, Brown-out Reset ---- 0000 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx 1111 1111 0000 q000 --00 0101 ---- ---0 0--1 11q0 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx xxxx xxxx 00-0 0000 -000 0000 0-00 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets ---- 0000 N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu ---u uuuu 0000 0000 uuuu uuuu 1111 1111 0000 q000 --00 0101 ---- ---0 0--q qquu uuuu uuuu uuuu uuuu u0uu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu uuuu uuuu 00-0 0000 -000 0000 0-00 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 Wake-up via WDT or Interrupt ---- uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu qquu --uu uuuu ---- ---u u--u qquu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 -uuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu -uuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON LVDCON WDTCON RCON
(4)
TMR1H TMR1L T1CON TMR2 PR2 T2CON ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON PWM1CON ECCPAS
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 5 of PORTA is enabled if MCLR is disabled.
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1220 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 1320 Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx 0-00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 000x -1-1 0-00 0000 0000 0000 0000 0000 0000 xx-0 x000 1--1 -110--0 -000--0 -00-111 -111 -000 -000 -000 -000 --00 0000 1111 1111 11-1 1111(5) xxxx xxxx xx-x xxxx(5) xxxx xxxx xx0x 0000(5,6) MCLR Resets WDT Reset RESET Instruction Stack Resets uuuu uuuu uuuu uuuu u-uu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 000x -1-1 0-00 0000 0000 0000 0000 0000 0000 uu-0 u000 1--1 -110--0 -000--0 -00-111 -111 -000 -000 -000 -000 --00 0000 1111 1111 11-1 1111(5) uuuu uuuu uu-u uuuu(5) uuuu uuuu uu0u 0000(5,6) Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -u-u u-uu uuuu uuuu uuuu uuuu 0000 0000 uu-0 u000 u--u -uuu--u -uu-(1) u--u -uu-uuu -uuu -uuu -uuu(1) -uuu -uuu --uu uuuu uuuu uuuu uu-u uuuu(5) uuuu uuuu uu-u uuuu(5) uuuu uuuu uuuu uuuu(5,6)
TMR3H TMR3L T3CON SPBRGH SPBRG RCREG TXREG TXSTA RCSTA BAUDCTL EEADR EEDATA EECON2 EECON1 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 OSCTUNE TRISB TRISA(5) LATB LATA(5) PORTB PORTA(5,6)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 5 of PORTA is enabled if MCLR is disabled.
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FIGURE 4-3:
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 0V 1V
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST TPLL
OST TIME-OUT
PLL TIME-OUT INTERNAL RESET
Note:
TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer.
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5.0 MEMORY ORGANIZATION
5.1 Program Memory Organization
There are three memory types in Enhanced MCU devices. These memory types are: * Program Memory * Data RAM * Data EEPROM Data and program memory use separate busses, which allows for concurrent access of these types. Additional detailed information for Flash program memory and data EEPROM is provided in Section 6.0 "Flash Program Memory" and Section 7.0 "Data EEPROM Memory", respectively. A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all `0's (a NOP instruction). The PIC18F1220 has 4 Kbytes of Flash memory and can store up to 2,048 single-word instructions. The PIC18F1320 has 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory maps for the PIC18F1220 and PIC18F1320 devices are shown in Figure 5-1 and Figure 5-2, respectively.
FIGURE 5-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18F1220
FIGURE 5-2:
PROGRAM MEMORY MAP AND STACK FOR PIC18F1320
PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1
* * *
PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1
* * *
Stack Level 31 Reset Vector 0000h
Stack Level 31 Reset Vector 0000h
High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory
High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h
0FFFh 1000h
On-Chip Program Memory 1FFFh User Memory Space 2000h
Read `0'
Read `0'
1FFFFFh 200000h
1FFFFFh 200000h
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DS39605F-page 41
User Memory Space
PIC18F1220/1320
5.2 Return Address Stack
5.2.2
The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit stack pointer, with the Stack Pointer initialized to 00000B after all Resets. There is no RAM associated with Stack Pointer, 00000B. This is only a Reset value. During a CALL type instruction, causing a push onto the stack, the Stack Pointer is first incremented and the RAM location pointed to by the Stack Pointer (STKPTR) register is written with the contents of the PC (already pointing to the instruction following the CALL). During a RETURN type instruction, causing a pop from the stack, the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of-stack Special File Registers. Data can also be pushed to or popped from the stack using the top-of-stack SFRs. Status bits indicate if the stack is full, has overflowed or underflowed.
RETURN STACK POINTER (STKPTR)
The STKPTR register (Register 5-1) contains the stack pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. At Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVR (Stack Overflow Reset Enable) configuration bit. (Refer to Section 19.1 "Configuration Bits" for a description of the device configuration bits.) If STVR is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVR is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.
5.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption.
FIGURE 5-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack 11111 11110 11101 TOSU 00h TOSH 1Ah TOSL 34h Top-of-Stack 00011 001A34h 00010 000D58h 00001 00000 STKPTR<4:0> 00010
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REGISTER 5-1: STKPTR REGISTER
R/C-0 STKFUL bit 7 bit 7(1) STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as `0' SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented `0' = Bit is cleared C = Clearable only bit x = Bit is unknown R/C-0 STKUNF U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0
bit 6(1)
bit 5 bit 4-0
5.2.3
PUSH AND POP INSTRUCTIONS
5.2.4
STACK FULL/UNDERFLOW RESETS
Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the Stack Pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place data or a return address on the stack. The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value.
These Resets are enabled by programming the STVR bit in Configuration Register 4L. When the STVR bit is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. When the STVR bit is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset.
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
5.3 Fast Register Stack 5.4 PCL, PCLATH and PCLATU
A "fast return" option is available for interrupts. A fast register stack is provided for the Status, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers, if the RETFIE, FAST instruction is used to return from the interrupt. All interrupt sources will push values into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. Users must save the key registers in software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. If no interrupts are used, the fast register stack can be used to restore the Status, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a CALL LABEL, FAST instruction must be executed to save the Status, WREG and BSR registers to the fast register stack. A RETURN, FAST instruction is then executed to restore these registers from the fast register stack. Example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may be performed through the PCLATU register. The contents of PCLATH and PCLATU will be transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.8.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSB of PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter.
EXAMPLE 5-1:
CALL SUB1, FAST
FAST REGISTER STACK CODE EXAMPLE
;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK
* * SUB1 * * RETURN, FAST
;RESTORE VALUES SAVED ;IN FAST REGISTER STACK
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5.5 Clocking Scheme/Instruction Cycle 5.6 Instruction Flow/Pipelining
An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-2). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-4.
FIGURE 5-4:
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC Mode)
PC PC + 2 PC + 4 Internal Phase Clock
Execute INST (PC - 2) Fetch INST (PC)
Execute INST (PC) Fetch INST (PC + 2)
Execute INST (PC + 2) Fetch INST (PC + 4)
EXAMPLE 5-2:
INSTRUCTION PIPELINE FLOW
TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h 2. MOVWF PORTB 3. BRA 4. BSF SUB_1
Fetch 1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed.
(c) 2007 Microchip Technology Inc.
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5.7 Instructions in Program Memory
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 5-5 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read `0' (see Section 5.4 "PCL, PCLATH and PCLATU"). The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-5 shows how the instruction `GOTO 000006h' is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 20.0 "Instruction Set Summary" provides further details of the instruction set.
FIGURE 5-5:
INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1 Program Memory Byte Locations LSB = 0 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h
Instruction 1: Instruction 2: Instruction 3:
MOVLW GOTO MOVFF
055h 000006h 123h, 456h
0Fh EFh F0h C1h F4h
55h 03h 00h 23h 56h
5.7.1
TWO-WORD INSTRUCTIONS
PIC18F1220/1320 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to `1's and is decoded as a NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the second word of the
instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that results in a skip operation. A program example that demonstrates this concept is shown in Example 5-3. Refer to Section 20.0 "Instruction Set Summary" for further details of the instruction set.
EXAMPLE 5-3:
CASE 1: Object Code
TWO-WORD INSTRUCTIONS
Source Code TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? ; Execute this word as a NOP REG3 ; continue code REG1, REG2 ; No, skip this word
0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 CASE 2: Object Code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000
Source Code TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? ; 2nd word of instruction REG3 ; continue code REG1, REG2 ; Yes, execute this word
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PIC18F1220/1320
5.8 Look-up Tables 5.9 Data Memory Organization
Look-up tables are implemented two ways: * Computed GOTO * Table Reads The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 5-6 shows the data memory organization for the PIC18F1220/1320 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented. The data memory contains Special Function Registers (SFR) and General Purpose Registers (GPR). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratch pad operations in the user's application. The SFRs start at the last location of Bank 15 (FFFh) and extend towards F80h. Any remaining space beyond the SFRs in the Bank may be implemented as GPRs. GPRs start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as `0's. The entire data memory may be accessed directly or indirectly. Direct addressing may require the use of the BSR register. Indirect addressing requires the use of a File Select Register (FSRn) and a corresponding Indirect File Operand (INDFn). Each FSR holds a 12-bit address value that can be used to access any location in the Data Memory map without banking. See Section 5.12 "Indirect Addressing, INDF and FSR Registers" for indirect addressing details. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 5.10 "Access Bank" provides a detailed description of the Access RAM.
5.8.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (see Example 5-4). A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions, that returns the value 0xnn to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSB = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required.
EXAMPLE 5-4:
MOVFW CALL 0xnn00 ADDWF RETLW RETLW RETLW . . .
COMPUTED GOTO USING AN OFFSET VALUE
OFFSET TABLE PCL 0xnn 0xnn 0xnn
ORG TABLE
5.8.2
TABLE READS/TABLE WRITES
A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to/from program memory, one byte at a time. The table read/table write operation is discussed further in Section 6.1 "Table Reads and Table Writes".
5.9.1
GENERAL PURPOSE REGISTER FILE
Enhanced MCU devices may have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Data RAM is available for use as GPR registers by all instructions. The second half of Bank 15 (F80h to FFFh) contains SFRs. All other banks of data memory contain GPRs, starting with Bank 0.
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FIGURE 5-6:
BSR<3:0> = 0000 00h Bank 0 FFh
DATA MEMORY MAP FOR PIC18F1220/1320 DEVICES
Data Memory Map Access RAM GPR 000h 07Fh 080h 0FFh
Access Bank 7Fh Access RAM High 80h (SFRs) FFh Access RAM Low 00h
= 0001 = 1110
Bank 1 to Bank 14
Unused Read `00h'
When a = 0, The BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When a = 1, The BSR specifies the Bank used by the instruction.
= 1111
00h Bank 15 FFh
Unused SFR
EFFh F00h F7Fh F80h FFFh
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5.9.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the "core" function and those related to the peripheral functions. Those registers related to the "core" are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as `0's.
TABLE 5-1:
Address FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FECh FEBh FEAh FE9h FE8h FE7h FE6h FE4h FE3h FE2h FE1h FE0h Note 1: 2:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F1220/1320 DEVICES
Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0
(2)
Address FDFh FDEh FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h
(2)
Name INDF2(2) POSTINC2(2)
(2)
Address FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h
Name CCPR1H CCPR1L CCP1CON -- -- -- -- -- PWM1CON ECCPAS -- -- TMR3H TMR3L T3CON SPBRGH SPBRG RCREG TXREG TXSTA RCSTA BAUDCTL EEADR EEDATA EECON2 EECON1 -- -- -- IPR2 PIR2 PIE2
Address F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h
Name IPR1 PIR1 PIE1 -- OSCTUNE -- -- -- -- -- -- -- TRISB TRISA -- -- -- -- -- -- -- LATB LATA -- -- -- -- -- -- -- PORTB PORTA
FDDh POSTDEC2
PREINC2(2) PLUSW2(2) FSR2H FSR2L STATUS TMR0H TMR0L T0CON -- OSCCON LVDCON WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON -- -- -- -- -- ADRESH ADRESL ADCON0 ADCON1 ADCON2
POSTINC0(2) PREINC0(2) PLUSW0(2) FSR0H FSR0L WREG INDF1
(2)
FEDh POSTDEC0(2)
POSTINC1(2) PREINC1(2) PLUSW1(2) FSR1H FSR1L BSR
FE5h POSTDEC1
Unimplemented registers are read as `0'. This is not a physical register.
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TABLE 5-2:
File Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON LVDCON WDTCON RCON Legend: Note 1: 2: 3: 4:
REGISTER FILE SUMMARY (PIC18F1220/1320)
Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---0 0000 0000 0000 0000 0000 Return Stack Pointer Holding Register for PC<20:16> 00-0 0000 ---0 0000 0000 0000 0000 0000 bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR0IE INTEDG1 -- INT0IE INTEDG2 INT2IE RBIE -- INT1IE TMR0IF TMR0IP -- INT0IF -- INT2IF RBIF RBIP INT1IF 0000 000x 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx Bank Select Register ---- 0000 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx OV Z DC C ---x xxxx 0000 0000 xxxx xxxx T0CS IRCF1 IVRST -- -- T0SE IRCF0 LVDEN -- RI PSA OSTS LVDL3 -- TO T0PS2 IOFS LVDL2 -- PD T0PS1 SCS1 LVDL1 -- POR T0PS0 SCS0 LVDL0 SWDTEN BOR 1111 1111 0000 q000 --00 0101 --- ---0 0--1 11q0 Details on page: 36, 42 36, 42 36, 42 36, 43 36, 44 36, 44 36, 44 36, 60 36, 60 36, 60 36, 60 36, 71 36, 71 36, 75 36, 76 36, 77 36, 53 36, 53 36, 53 36, 53 36, 53 36, 53 36, 53 36 36, 53 36, 53 36, 53 36, 53 36, 53 36, 53 36, 53 37, 52 37, 53 37, 53 37, 53 37, 53 37, 53 37, 53 37, 53 37, 55 37, 101 37, 101 37, 99 37, 17 37, 167 37, 180 35, 56, 84
Top-of-Stack Upper Byte (TOS<20:16>)
Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKFUL -- STKUNF -- -- bit 21(3)
Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- --
Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory- value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 offset by W (not a physical register) -- -- -- -- Indirect Data Memory Address Pointer 0 High
Indirect Data Memory Address Pointer 0 Low Byte Working Register Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 offset by W (not a physical register) -- -- -- -- Indirect Data Memory Address Pointer 1 High
Indirect Data Memory Address Pointer 1 Low Byte -- -- -- --
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 offset by W (not a physical register) -- -- -- -- Indirect Data Memory Address Pointer 2 High
Indirect Data Memory Address Pointer 2 Low Byte -- -- -- N
Timer0 Register High Byte Timer0 Register Low Byte TMR0ON IDLEN -- -- IPEN T08BIT IRCF2 -- -- --
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read `0' in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to `0'. Otherwise, RA5 reads `0'. This bit is read-only.
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TABLE 5-2:
File Name TMR1H TMR1L T1CON TMR2 PR2 T2CON ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON PWM1CON ECCPAS TMR3H TMR3L T3CON SPBRGH SPBRG RCREG TXREG TXSTA RCSTA BAUDCTL EEADR EEDATA EECON2 EECON1 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 OSCTUNE TRISB TRISA LATB LATA PORTB PORTA Legend: Note 1: 2: 3: 4:
REGISTER FILE SUMMARY (PIC18F1220/1320) (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx xxxx xxxx T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000 1111 1111 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx xxxx xxxx -- PCFG5 ACQT2 CHS2 PCFG4 ACQT1 CHS1 PCFG3 ACQT0 CHS0 PCFG2 ADCS2 GO/DONE PCFG1 ADCS1 ADON PCFG0 ADCS0 00-0 0000 -000 0000 0-00 0000 xxxx xxxx xxxx xxxx CCP1M3 PDC3 PSSAC1 CCP1M2 PDC2 PSSAC0 CCP1M1 PDC1 PSSBD1 CCP1M0 PDC0 PSSBD0 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 0000 0000 0000 0000 0000 0000 0000 0000 TXEN SREN -- SYNC CREN SCKP SENDB ADDEN BRG16 BRGH FERR -- TRMT OERR WUE TX9D RX9D ABDEN 0000 0010 0000 000x -1-1 0-00 0000 0000 0000 0000 0000 0000 WRERR -- -- -- -- -- -- TUN3 WREN LVDIP LVDIF LVDIE CCP1IP CCP1IF CCP1IE TUN2 WR TMR3IP TMR3IF TMR3IE TMR2IP TMR2IF TMR2IE TUN1 RD -- -- -- TMR1IP TMR1IF TMR1IE TUN0 xx-0 x000 1--1 -110--0 -000--0 -00-111 -111 -000 -000 -000 -000 --00 0000 1111 1111 11-1 1111 xxxx xxxx -- RA5(4) Read/Write PORTA Data Latch xx-x xxxx xxxx xxxx xx0x 0000 Details on page: 37, 108 37, 108 37, 103 37, 109 37, 109 37, 109 37, 164 37, 164 37, 155 37, 156 37, 157 37. 116 37, 116 37, 115 37, 126 37, 127 38, 113 38, 113 38, 111 38 38, 135 38, 143, 142 38, 140, 142 38, 132 38, 133 38 38, 67 38, 70 38, 58, 67 38, 59, 68 38, 83 38, 79 38, 81 38, 82 38, 78 38, 80 38, 15 38, 98 38, 89 38, 98 38, 89 38, 98 38, 89
Timer1 Register High Byte Timer1 Register Low Byte RD16 T1RUN
Timer2 Register Timer2 Period Register -- TOUTPS3
A/D Result Register High Byte A/D Result Register Low Byte VCFG1 -- ADFM VCFG0 PCFG6 --
Capture/Compare/PWM Register 1 High Byte Capture/Compare/PWM Register 1 Low Byte P1M1 PRSEN ECCPASE P1M0 PDC6 ECCPAS2 DC1B1 PDC5 ECCPAS1 DC1B0 PDC4 ECCPAS0
Timer3 Register High Byte Timer3 Register Low Byte RD16 --
EUSART Baud Rate Generator High Byte EUSART Baud Rate Generator Low Byte EUSART Receive Register EUSART Transmit Register CSRC SPEN -- TX9 RX9 RCIDL
EEPROM Address Register EEPROM Data Register EEPROM Control Register 2 (not a physical register) EEPGD OSCFIP OSCFIF OSCFIE -- -- -- -- TRISA7(2) CFGS -- -- -- ADIP ADIF ADIE -- TRISA6(1) -- -- -- -- RCIP RCIF RCIE TUN5 FREE EEIP EEIF EEIE TXIP TXIF TXIE TUN4
Data Direction Control Register for PORTB -- Data Direction Control Register for PORTA
Read/Write PORTB Data Latch LATA<7>(2) LATA<6>(1) RA7(2) RA6(1)
Read PORTB pins, Write PORTB Data Latch Read PORTA pins, Write PORTA Data Latch
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read `0' in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to `0'. Otherwise, RA5 reads `0'. This bit is read-only.
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5.10 Access Bank 5.11 Bank Select Register (BSR)
The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This data memory region can be used for: * * * * * Intermediate computational values Local variables of subroutines Faster context saving/switching of variables Common variables Faster evaluation/control of SFRs (no banking) The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into as many as sixteen banks. When using direct addressing, the BSR should be configured for the desired bank. BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read `0's and writes will have no effect (see Figure 5-7). A MOVLB instruction has been provided in the instruction set to assist in selecting banks. If the currently selected bank is not implemented, any read will return all `0's and all writes are ignored. The Status register bits will be set/cleared as appropriate for the instruction performed. Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM. A MOVFF instruction ignores the BSR, since the 12-bit addresses are embedded into the instruction word. Section 5.12 "Indirect Addressing, INDF and FSR Registers" provides a description of indirect addressing, which allows linear addressing of the entire RAM space.
The Access Bank is comprised of the last 128 bytes in Bank 15 (SFRs) and the first 128 bytes in Bank 0. These two sections will be referred to as Access RAM High and Access RAM Low, respectively. Figure 5-6 indicates the Access RAM areas. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register or in the Access Bank. This bit is denoted as the `a' bit (for access bit). When forced in the Access Bank (a = 0), the last address in Access RAM Low is followed by the first address in Access RAM High. Access RAM High maps the Special Function Registers, so these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits.
FIGURE 5-7:
DIRECT ADDRESSING
Direct Addressing
From Opcode(3)
BSR<7:4>
BSR<3:0>
7
0
0
0
0
0
Location Select(3) 00h 000h 01h 100h 0Eh E00h 0Fh F00h
Bank Select(2)
Data Memory(1)
0FFh
1FFh
EFFh
FFFh
Bank 0
Bank 1
Bank 14
Bank 15
Note 1: For register file map detail, see Table 5-1. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
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5.12 Indirect Addressing, INDF and FSR Registers
If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all `0's are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected.
Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 5-8 shows how the fetched instruction is modified prior to being executed. Indirect addressing is possible by using one of the INDF registers. Any instruction, using the INDF register, actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0), will read 00h. Writing to the INDF register indirectly, results in a no operation (NOP). The FSR register contains a 12-bit address, which is shown in Figure 5-9. The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register (FSRn is a pointer). This is indirect addressing. Example 5-5 shows a simple use of indirect addressing to clear the RAM in Bank 1 (locations 100h-1FFh) in a minimum number of instructions.
5.12.1
INDIRECT ADDRESSING OPERATION
Each FSR register has an INDF register associated with it, plus four additional register addresses. Performing an operation using one of these five registers determines how the FSR will be modified during indirect addressing. When data access is performed using one of the five INDFn locations, the address selected will configure the FSRn register to: * Do nothing to FSRn after an indirect access (no change) - INDFn * Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn * Auto-increment FSRn after an indirect access (post-increment) - POSTINCn * Auto-increment FSRn before an indirect access (pre-increment) - PREINCn * Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) - PLUSWn When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the Status register. For example, if the indirect address causes the FSR to equal `0', the Z bit will not be set. Auto-incrementing or auto-decrementing an FSR affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a stack pointer, in addition to its uses for table operations in data memory. Each FSR has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the signed value in the WREG register and the value in FSR to form the address before an indirect access. The FSR value is not changed. The WREG offset range is -128 to +127. If an FSR register contains a value that points to one of the INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (Status bits are not affected). If an indirect addressing write is performed when the target address is an FSRnH or FSRnL register, the data is written to the FSR register, but no pre- or post-increment/ decrement is performed.
EXAMPLE 5-5:
HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING
FSR0,0x100 POSTINC0 ; ; ; ; ; ; ; ; Clear INDF register then inc pointer All done with Bank1? NO, clear next YES, continue
NEXT
LFSR CLRF
BTFSS GOTO CONTINUE
FSR0H, 1 NEXT
There are three indirect addressing registers. To address the entire data memory space (4096 bytes), these registers are 12-bit wide. To store the 12 bits of addressing information, two 8-bit registers are required: 1. 2. 3. FSR0: composed of FSR0H:FSR0L FSR1: composed of FSR1H:FSR1L FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data. If an instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads the data from the address pointed to by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used.
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FIGURE 5-8: INDIRECT ADDRESSING OPERATION
RAM 0h
Instruction Executed Opcode Address FFFh 12 File Address = Access of an Indirect Addressing Register
BSR<3:0> Instruction Fetched Opcode 4
12 8 File
12
FSR
FIGURE 5-9:
INDIRECT ADDRESSING
Indirect Addressing
FSRnH:FSRnL 3 11 Location Select 0 7 0 0
0000h
Data Memory(1)
0FFFh Note 1: For register file map detail, see Table 5-1.
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5.13 Status Register
The Status register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the Status register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed. Therefore, the result of an instruction with the Status register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (`000u u1uu'). It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the Status register, because these instructions do not affect the Z, C, DC, OV or N bits in the Status register. For other instructions that do not affect Status bits, see the instruction set summaries in Table 20-1. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction.
REGISTER 5-2:
STATUS REGISTER
U-0 -- bit 7 U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC R/W-x C bit 0
bit 7-5 bit 4
Unimplemented: Read as `0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register.
bit 3
bit 2
bit 1
bit 0
C: Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register.
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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5.14 RCON Register
The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. Note 1: If the BOR configuration bit is set (Brownout Reset enabled), the BOR bit is `1' on a Power-on Reset. After a Brown-out Reset has occurred, the BOR bit will be cleared and must be set by firmware to indicate the occurrence of the next Brown-out Reset. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected.
REGISTER 5-3:
RCON REGISTER
R/W-0 IPEN bit 7 U-0 -- U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0
bit 7
IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as `0' RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Cleared by execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5 bit 4
bit 3
bit 2
bit 1
bit 0
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6.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A "Bulk Erase" operation may not be issued from user code. While writing or erasing program memory, instruction fetches cease until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into TABLAT in the data RAM space. Figure 6-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from TABLAT in the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 "Writing to Flash Program Memory". Figure 6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned (TBLPTRL<0> = 0). The EEPROM on-chip timer controls the write and erase times. The write and erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations.
6.1
Table Reads and Table Writes
In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT)
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL
Program Memory Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
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FIGURE 6-2: TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 "Writing to Flash Program Memory".
6.2
Control Registers
Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers
The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled - the WR bit cannot be set while the WREN bit is clear. This process helps to prevent accidental writes to memory due to errant (unexpected) code execution. Firmware should keep the WREN bit clear at all times, except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress. The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can check the WRERR bit and rewrite the location. It will be necessary to reload the data and address registers (EEDATA and EEADR) as these registers have cleared as a result of the Reset. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.3 "Reading the Flash Program Memory" regarding table reads. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software.
6.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit, CFGS, determines if the access will be to the configuration registers, or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The FREE bit controls program memory erase operations. When the FREE bit is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled.
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REGISTER 6-1: EECON1 REGISTER
R/W-x EEPGD bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access configuration registers 0 = Access program Flash or data EEPROM memory Unimplemented: Read as `0' FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation - TBLPTR<5:0> are ignored) 0 = Perform write only WRERR: EEPROM Error Flag bit 1 = A write operation was prematurely terminated (any Reset during self-timed programming) 0 = The write operation completed normally Note: bit 2 When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 6
bit 5 bit 4
bit 3
WREN: Write Enable bit 1 = Allows erase or write cycles 0 = Inhibits erase or write cycles WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle completed RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Legend: R = Readable bit W = Writable bit x = Bit is unknown S = Settable only -n = Value at POR U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared
bit 1
bit 0
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6.2.2 TABLAT - TABLE LATCH REGISTER 6.2.4 TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The table latch is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program or configuration memory into TABLAT. When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight program memory holding registers is written to. When the timed write to program memory (long write) begins, the 19 MSbs of the Table Pointer (TBLPTR<21:3>) will determine which program memory block of 8 bytes is written to (TBLPTR<2:0> are ignored). For more detail, see Section 6.5 "Writing to Flash Program Memory". When an erase of program memory is executed, the 16 MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations.
6.2.3
TBLPTR - TABLE POINTER REGISTER
The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. Setting the 22nd bit allows access to the device ID, the user ID and the configuration bits. The Table Pointer (TBLPTR) register is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low-order 21 bits.
TABLE 6-1:
Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+*
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write
FIGURE 6-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0
ERASE - TBLPTR<21:6> LONG WRITE - TBLPTR<21:3> READ or WRITE - TBLPTR<21:0>
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6.3 Reading the Flash Program Memory
The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT.
The TBLRD instruction is used to retrieve data from program memory and place it into data RAM. Table reads from program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing a TBLRD instruction places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
Odd (High) Byte
Even (Low) Byte
TBLPTR LSB = 1 Instruction Register (IR) TABLAT Read Register
TBLPTR LSB = 0
EXAMPLE 6-1:
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD
READING A FLASH PROGRAM MEMORY WORD
CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word
TBLRD*+ MOVFW MOVWF TBLRD*+ MOVFW MOVWF
TABLAT WORD_EVEN TABLAT WORD_ODD
; read into TABLAT and increment TBLPTR ; get data ; read into TABLAT and increment TBLPTR ; get data
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6.4 Erasing Flash Program Memory
6.4.1
The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The CFGS bit must be clear to access program Flash and data EEPROM memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. The WR bit is set as part of the required instruction sequence (as shown in Example 6-2) and starts the actual erase operation. It is not necessary to load the TABLAT register with any data as it is ignored. For protection, the write initiate sequence using EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.
FLASH PROGRAM MEMORY ERASE SEQUENCE
The sequence of events for erasing a block of internal program memory location is: 1. 2. Load Table Pointer with address of row being erased. Set the EECON1 register for the erase operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN bit to enable writes; * set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the row erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts.
3. 4. 5. 6. 7. 8. 9.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EECON1, EECON1, INTCON, 55h EECON2 AAh EECON2 EECON1, EEPGD WREN FREE GIE ; load TBLPTR with the base ; address of the memory block
ERASE_ROW BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF ; ; ; ; point to FLASH program memory enable write to memory enable Row Erase operation disable interrupts
; write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts
Required Sequence
WR
INTCON, GIE
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6.5 Writing to Flash Program Memory
The programming block size is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction must be executed 8 times for each programming operation. All of the table write operations will essentially be short writes, because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT Write Register
8
TBLPTR = xxxxx0 TBLPTR = xxxxx1
8
TBLPTR = xxxxx2
8
TBLPTR = xxxxx7
8
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
6.5.1
FLASH PROGRAM MEMORY WRITE SEQUENCE
The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer with address being erased. Do the row erase procedure (see Section 6.4.1 "Flash Program Memory Erase Sequence"). Load Table Pointer with address of first byte being written. Write the first 8 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN bit to enable byte writes.
8. 9. 10. 11. 12. 13. 14. 15. 16.
Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts. Repeat steps 6-14 seven times to write 64 bytes. Verify the memory (table read).
This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3.
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EXAMPLE 6-3:
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_BLOCK TBLRD*+ MOVF MOVWF DECFSZ GOTO MODIFY_WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF WRITE_BUFFER_BACK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF PROGRAM_LOOP MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, CFGS EECON1, EEPGD EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 AAh EECON2 EECON1, WR INTCON, GIE 8 COUNTER_HI BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L 8 COUNTER ; load TBLPTR with the base ; address of the memory block DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to buffer TABLAT, W POSTINC0 COUNTER READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data and increment FSR0 done? repeat
WRITING TO FLASH PROGRAM MEMORY
D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block ; point to buffer
; Load TBLPTR with the base ; address of the memory block
; 6 LSB = 0
; update buffer word and increment FSR0 ; update buffer word
; 6 LSB = 0 ; ; ; ; ; ; ; point to PROG/EEPROM memory point to FLASH program memory enable write to memory enable Row Erase operation disable interrupts Required sequence write 55H
; write AAH ; start erase (CPU stall) ; re-enable interrupts ; number of write buffer groups of 8 bytes ; point to buffer
; number of bytes in holding register
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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
; ; ; ; get low byte of buffer data and increment FSR0 present data to table latch short write to internal TBLWT holding register, increment TBLPTR ; loop until buffers are full WRITE_WORD_TO_HREGS MOVF POSTINC0, W MOVWF TABLAT TBLWT+*
DECFSZ COUNTER GOTO WRITE_WORD_TO_HREGS PROGRAM_MEMORY BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1, WR NOP BSF INTCON, GIE DECFSZ COUNTER_HI GOTO PROGRAM_LOOP BCF EECON1, WREN
; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ; loop until done ; disable write to memory
6.5.2
WRITE VERIFY
6.6
Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.
Flash Program Operation During Code Protection
See Section 19.0 "Special Features of the CPU" for details on code protection of Flash program memory.
6.5.3
UNEXPECTED TERMINATION OF WRITE OPERATION
If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location.
TABLE 6-2:
Name TBLPTRU Bit 7 --
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Bit 6 -- Bit 5 bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 INTE FREE EEIP EEIF EEIE RBIE WRERR -- -- -- TMR0IF WREN LVDIP LVDIF LVDIE INTF WR TMR3IP TMR3IF TMR3IE RBIF RD -- -- -- 0000 000x 0000 000u
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) TABLAT INTCON EECON2 EECON1 IPR2 PIR2 PIE2 Legend: Program Memory Table Latch GIE/GIEH PEIE/GIEL TMR0IE EEPGD OSCFIP OSCFIF OSCFIE CFGS -- -- -- -- -- -- -- EEPROM Control Register 2 (not a physical register)
--
--
xx-0 x000 uu-0 u000 1--1 -11- 1--1 -110--0 -00- 0--0 -000--0 -00- 0--0 -00-
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access.
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NOTES:
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7.0 DATA EEPROM MEMORY
The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: * * * * EECON1 EECON2 EEDATA EEADR Control bit, CFGS, determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled - the WR bit cannot be set while the WREN bit is clear. This mechanism helps to prevent accidental writes to memory due to errant (unexpected) code execution. Firmware should keep the WREN bit clear at all times, except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress. The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR), as these registers have cleared as a result of the Reset. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 "Table Reads and Table Writes" regarding table reads. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software.
The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. These devices have 256 bytes of data EEPROM with an address range from 00h to FFh. The EEPROM data memory is rated for high erase/ write cycle endurance. A byte write automatically erases the location and writes the new data (erasebefore-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip to chip. Please refer to parameter D122 (Table 22-1 in Section 22.0 "Electrical Characteristics") for exact limits.
7.1
EEADR
The address register can address 256 bytes of data EEPROM.
7.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed.
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REGISTER 7-1: EECON1 REGISTER
R/W-x EEPGD bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access program Flash or data EEPROM memory Unimplemented: Read as `0' FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only WRERR: EEPROM Error Flag bit 1 = A write operation was prematurely terminated (MCLR or WDT Reset during self-timed erase or program operation) 0 = The write operation completed normally Note: bit 2 When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 6
bit 5 bit 4
bit 3
WREN: Erase/Write Enable bit 1 = Allows erase/write cycles 0 = Inhibits erase/write cycles WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle, or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is completed RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Legend: R = Readable bit W = Writable bit x = Bit is unknown S = Settable only -n = Value at POR U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared
bit 1
bit 0
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7.3 Reading the Data EEPROM Memory
After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software.
To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).
7.4
Writing to the Data EEPROM Memory
7.5
Write Verify
To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware.
Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.
7.6
Protection Against Spurious Write
There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction.
EXAMPLE 7-1:
MOVLW MOVWF BCF BSF MOVF
DATA EEPROM READ
DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, RD EEDATA, W ; ; ; ; ; Data Memory Address to read Point to DATA memory EEPROM Read W = EEDATA
EXAMPLE 7-2:
MOVLW MOVWF MOVLW MOVWF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF SLEEP BCF
DATA EEPROM WRITE
DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, WREN INTCON, GIE 55h EECON2 AAh EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; ; ; ; ; ; ; ; ; Data Memory Address to write Data Memory Value to write Point to DATA memory Enable writes Disable Interrupts Write 55h Write AAh Set WR bit to begin write Enable Interrupts
Required Sequence
EECON1, WREN
; Wait for interrupt to signal write complete ; Disable writes
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7.7 Operation During Code-Protect 7.8 Using the Data EEPROM
Data EEPROM memory has its own code-protect bits in configuration words. External read and write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect configuration bit. Refer to Section 19.0 "Special Features of the CPU" for additional information. The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 7-3. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124.
EXAMPLE 7-3:
CLRF BCF BCF BCF BSF Loop BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA BCF BSF
DATA EEPROM REFRESH ROUTINE
EEADR EECON1, EECON1, INTCON, EECON1, CFGS EEPGD GIE WREN ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write AAh Set WR bit to begin write Wait for write to complete
EECON1, RD 55h EECON2 AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F Loop EECON1, WREN INTCON, GIE
; Increment address ; Not zero, do it again ; Disable writes ; Enable interrupts
TABLE 7-1:
Name INTCON EEADR EEDATA EECON2 EECON1 IPR2 PIR2 PIE2 Bit 7
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Bit 6 PEIE/GIEL Bit 5 TMR0IE Bit 4 INTE Bit 3 RBIE Bit 2 TMR0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR Value on all other Resets
GIE/GIEH
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 -- --
EEPROM Address Register EEPROM Data Register EEPROM Control Register 2 (not a physical register) EEPGD OSCFIP OSCFIF OSCFIE CFGS -- -- -- -- -- -- -- FREE EEIP EEIF EEIE WRERR -- -- -- WREN LVDIP LVDIF LVDIE WR TMR3IP TMR3IF TMR3IE RD -- -- --
xx-0 x000 uu-0 u000 1--1 -11- 1--1 -110--0 -00- 0--0 -000--0 -00- 0--0 -00-
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access.
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8.0
8.1
8 x 8 HARDWARE MULTIPLIER
Introduction
Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: * Higher computational throughput * Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors. Table 8-1 shows a performance comparison between Enhanced devices using the single-cycle hardware multiply and performing the same function without the hardware multiply.
An 8 x 8 hardware multiplier is included in the ALU of the PIC18F1220/1320 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the Status register.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON
Multiply Method Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 28 52 35 Cycles (Max) 69 1 91 6 242 28 254 40 Time @ 40 MHz 6.9 s 100 ns 9.1 s 600 ns 24.2 s 2.8 s 25.4 s 4 s @ 10 MHz 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 11.2 s 102.6 s 16 s @ 4 MHz 69 s 1 s 91 s 6 s 242 s 28 s 254 s 40 s
8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed
8.2
Operation
EXAMPLE 8-2:
MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF ARG1, W ARG2 ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F
Example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 8-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done.
8 x 8 SIGNED MULTIPLY ROUTINE
; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1
EXAMPLE 8-1:
MOVF MULWF ARG1, W ARG2
8 x 8 UNSIGNED MULTIPLY ROUTINE
; ; ARG1 * ARG2 -> ; PRODH:PRODL
; Test Sign Bit ; PRODH = PRODH ; - ARG2
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Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0.
EQUATION 8-2:
16 x 16 SIGNED MULTIPLICATION ALGORITHM
EQUATION 8-1:
16 x 16 UNSIGNED MULTIPLICATION ALGORITHM
RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L)
RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) + (-1 * ARG1H<7> * ARG2H:ARG2L * 216)
EXAMPLE 8-4:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; BTFSS BRA MOVF SUBWF MOVF SUBWFB ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE :
16 x 16 SIGNED MULTIPLY ROUTINE
; ARG1L * ARG2L -> ; PRODH:PRODL ; ;
EXAMPLE 8-3:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC
16 x 16 UNSIGNED MULTIPLY ROUTINE
; ARG1L * ARG2L -> ; PRODH:PRODL ; ;
ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3
ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3,F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F
; ARG1H * ARG2H -> ; PRODH:PRODL ; ;
; ARG1H * ARG2H -> ; PRODH:PRODL ; ;
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H -> PRODH:PRODL Add cross products
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H -> PRODH:PRODL Add cross products
ARG1H * ARG2L -> PRODH:PRODL Add cross products
ARG1H * ARG2L -> PRODH:PRODL Add cross products
Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the arguments, each argument pairs' Most Significant bit (MSb) is tested and the appropriate subtractions are done.
; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ;
ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3
; ARG1H:ARG1L neg? ; no, done ; ; ;
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9.0 INTERRUPTS
The PIC18F1220/1320 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2 PIE1, PIE2 IPR1, IPR2 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL, if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.
It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, each interrupt source has three bits to control its operation. The functions of these bits are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority (INT0 has no priority bit and is always high priority) The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits.
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FIGURE 9-1: INTERRUPT LOGIC
TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP
Wake-up if in Low-Power Mode
Interrupt to CPU Vector to Location 0008h
INT0IF INT0IE
ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation
GIEH/GIE IPEN IPEN GIEL/PEIE IPEN
INT0IF INT0IE TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Additional Peripheral Interrupts INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Interrupt to CPU Vector to Location 0018h
ADIF ADIE ADIP RCIF RCIE RCIP
GIEL\PEIE GIE\GIEH
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9.1 INTCON Registers
Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
REGISTER 9-1:
INTCON REGISTER
R/W-0 GIE/GIEH bit 7 R/W-0 PEIE/GIEL R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 9-2: INTCON2 REGISTER
R/W-1 RBPU bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge Unimplemented: Read as `0' TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INTEDG0 R/W-1 INTEDG1 R/W-1 INTEDG2 U-0 -- R/W-1 TMR0IP U-0 -- R/W-1 RBIP bit 0
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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REGISTER 9-3: INTCON3 REGISTER
R/W-1 INT2IP bit 7 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt Unimplemented: Read as `0' INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INT1IP U-0 -- R/W-0 INT2IE R/W-0 INT1IE U-0 -- R/W-0 INT2IF R/W-0 INT1IF bit 0
bit 6
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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9.2 PIR Registers
The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
U-0 -- bit 7 R/W-0 ADIF R-0 RCIF R-0 TXIF U-0 -- R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 7 bit 6
Unimplemented: Read as `0' ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full Unimplemented: Read as `0' CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 OSCFIF bit 7 bit 7 U-0 -- U-0 -- R/W-0 EEIF U-0 -- R/W-0 LVDIF R/W-0 TMR3IF U-0 -- bit 0
OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating Unimplemented: Read as `0' EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started Unimplemented: Read as `0' LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low-Voltage Detect trip point TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow Unimplemented: Read as `0' Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5 bit 4
bit 3 bit 2
bit 1
bit 0
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9.3 PIE Registers
The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
REGISTER 9-6:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 -- bit 7 R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE U-0 -- R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
bit 7 bit 6
Unimplemented: Read as `0' ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt Unimplemented: Read as `0' CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 OSCFIE bit 7 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 EEIE U-0 -- R/W-0 LVDIE R/W-0 TMR3IE U-0 -- bit 0
bit 6-5 bit 4
bit 3 bit 2
bit 1
bit 0
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9.4 IPR Registers
The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
REGISTER 9-8:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0 -- bit 7 R/W-1 ADIP R/W-1 RCIP R/W-1 TXIP U-0 -- R/W-1 CCP1IP R/W-1 TMR2IP R/W-1 TMR1IP bit 0
bit 7 bit 6
Unimplemented: Read as `0' ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority
bit 5
bit 4
bit 3 bit 2
Unimplemented: Read as `0' CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 1
bit 0
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REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 OSCFIP bit 7 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-1 EEIP U-0 -- R/W-1 LVDIP R/W-1 TMR3IP U-0 -- bit 0
bit 6-5 bit 4
bit 3 bit 2
bit 1
bit 0
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9.5 RCON Register
The RCON register contains bits used to determine the cause of the last Reset or wake-up from a low-power mode. RCON also contains the bit that enables interrupt priorities (IPEN).
REGISTER 9-10:
RCON REGISTER
R/W-0 IPEN bit 7 U-0 -- U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0
bit 7
IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as `0' RI: RESET Instruction Flag bit For details of bit operation, see Register 5-3. TO: Watchdog Time-out Flag bit For details of bit operation, see Register 5-3. PD: Power-down Detection Flag bit For details of bit operation, see Register 5-3. POR: Power-on Reset Status bit For details of bit operation, see Register 5-3. BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-3. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5 bit 4 bit 3 bit 2 bit 1 bit 0
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9.6 INTn Pin Interrupts 9.7 TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered: either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE. Flag bit, INTxF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the processor from low-power modes if bit INTxE was set prior to going into low-power modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a high priority interrupt source. In 8-bit mode (which is the default), an overflow (FFh 00h) in the TMR0 register will set flag bit, TMR0IF. In 16-bit mode, an overflow (FFFFh 0000h) in the TMR0H:TMR0L registers will set flag bit, TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 11.0 "Timer0 Module" for further details on the Timer0 module.
9.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>).
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on the stack. Additionally, the WREG, Status and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 5.3 "Fast Register Stack"), the user may need to save the WREG, Status and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, Status and BSR registers during an Interrupt Service Routine.
EXAMPLE 9-1:
MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere
W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS
; Restore BSR ; Restore WREG ; Restore STATUS
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NOTES:
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10.0 I/O PORTS
Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (data direction register) * PORT register (reads the levels on the pins of the device) * LAT register (output latch) The Data Latch (LATA) register is useful for readmodify-write operations on the value that the I/O pins are driving. A simplified model of a generic I/O port without the interfaces to other peripherals is shown in Figure 10-1. The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The sixth pin of PORTA (MCLR/VPP/RA5) is an input only pin. Its operation is controlled by the MCLRE configuration bit in Configuration Register 3H (CONFIG3H<7>). When selected as a port pin (MCLRE = 0), it functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device's Master Clear input. In either configuration, RA5 also functions as the programming voltage input during programming. Note: On a Power-on Reset, RA5 is enabled as a digital input only if Master Clear functionality is disabled.
FIGURE 10-1:
GENERIC I/O PORT OPERATION
RD LAT Data Bus WR LAT or Port
Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in Configuration Register 1H (see Section 19.1 "Configuration Bits" for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as `0'. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the LVD input. The operation of pins RA3:RA0 as A/D converter inputs is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). Note: On a Power-on Reset, RA3:RA0 are configured as analog inputs and read as `0'. RA4 is always a digital pin.
D
Q I/O pin(1)
CK Data Latch D Q
WR TRIS
CK TRIS Latch Input Buffer
RD TRIS Q D EN EN RD Port Note 1: I/O pins have diode protection to VDD and VSS.
The RA4/T0CKI pin is a Schmitt Trigger input and an open-drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
EXAMPLE 10-1:
CLRF ; ; ; LATA ; ; ; 0x7F ; ADCON1 ; 0xD0 ; ; ; TRISA ; ; PORTA
INITIALIZING PORTA
Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<3:0> as outputs RA<7:4> as inputs
10.1
PORTA, TRISA and LATA Registers
CLRF
PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch.
MOVLW MOVWF MOVLW
MOVWF
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FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 PINS FIGURE 10-4: BLOCK DIAGRAM OF RA4/T0CKI PIN
RD LATA Data Bus WR LATA or PORTA
RD LATA Data Bus VDD CK Q P I/O pin(1) WR TRISA CK Q VSS TRIS Latch RD TRISA WR LATA or PORTA
D
Q
D
Q Q I/O pin(1)
CK
N
Data Latch D WR TRISA Analog Input Mode Q N
Data Latch D Q Q VSS Schmitt Trigger Input Buffer
CK
TRIS Latch
RD TRISA Q D EN RD PORTA To A/D Converter and LVD Modules Note 1:
Schmitt Trigger Input Buffer RD PORTA TMR0 Clock Input Note 1:
Q
D EN EN
I/O pins have protection diodes to VDD and VSS.
I/O pins have protection diodes to VDD and VSS.
FIGURE 10-3:
RA6 Enable Data Bus RD LATA
BLOCK DIAGRAM OF OSC2/CLKO/RA6 PIN
FIGURE 10-5:
RA7 Enable Data Bus RD LATA
BLOCK DIAGRAM OF OSC1/CLKI/RA7 PIN
To Oscillator
D WR LATA or PORTA
Q
VDD P
D WR LATA or PORTA
Q
VDD P
CK
Q
CK
Q
Data Latch D WR TRISA Q N I/O pin(1) WR TRISA Schmitt Trigger Input Buffer
Data Latch D Q N I/O pin(1)
CK
Q
VSS
CK
Q
VSS
TRIS Latch RD TRISA ECIO or RCIO Enable
TRIS Latch RD TRISA RA7 Enable
Schmitt Trigger Input Buffer
Q
D EN
Q
D EN
RD PORTA Note 1: I/O pins have protection diodes to VDD and VSS.
RD PORTA Note 1: I/O pins have protection diodes to VDD and VSS.
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FIGURE 10-6: MCLR/VPP/RA5 PIN BLOCK DIAGRAM
MCLRE Data Bus RD TRISA Schmitt Trigger RD LATA Latch Q D EN MCLR/VPP/RA5
RD PORTA High-Voltage Detect Internal MCLR Filter Low-Level MCLR Detect HV
TABLE 10-1:
Name RA0/AN0 RA1/AN1/LVDIN RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI MCLR/VPP/RA5
PORTA FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer ST ST ST ST ST ST ST ST Function Input/output port pin or analog input. Input/output port pin, analog input or Low-Voltage Detect input. Input/output port pin, analog input or VREF-. Input/output port pin, analog input or VREF+. Input/output port pin or external clock input for Timer0. Output is open-drain type. Master Clear input or programming voltage input (if MCLR is enabled); input only port pin or programming voltage input (if MCLR is disabled). OSC2, clock output or I/O pin. OSC1, clock input or I/O pin.
OSC2/CLKO/RA6 OSC1/CLKI/RA7
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2:
Name PORTA LATA TRISA ADCON1 Legend: Note 1: 2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 6 RA6(1) LATA6(1) PCFG6 Bit 5 RA5(2) -- -- Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR Value on all other Resets
Bit 7 RA7(1) LATA7 --
(1)
xx0x 0000 uu0u 0000 xx-x xxxx uu-u uuuu 11-1 1111 11-1 1111
LATA Data Output Register PORTA Data Direction Register
TRISA7(1) TRISA6(1)
PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as `0'. RA5 is an input only if MCLR is disabled.
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10.2 PORTB, TRISB and LATB Registers
This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF instruction). This will end the mismatch condition. Clear flag bit, RBIF.
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB.
b)
A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature.
EXAMPLE 10-2:
CLRF ; ; ; LATB ; ; ; 0x70 ; ADCON1 ; ; 0xCF ; ; TRISB ; ; ; PORTB
INITIALIZING PORTB
Initialize PORTB by clearing output data latches Alternate method to clear output data latches Set RB0, RB1, RB4 as digital I/O pins Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
FIGURE 10-7:
BLOCK DIAGRAM OF RB0/AN4/INT0 PIN
VDD Weak P Pull-up Q I/O pin(1)
CLRF
RBPU(2) Analog Input Mode Data Bus D WR LATB or PORTB
MOVLW MOVWF MOVLW
CK Data Latch D Q
MOVWF
WR TRISB
CK TRIS Latch
Pins RB0-RB2 are multiplexed with INT0-INT2; pins RB0, RB1 and RB4 are multiplexed with A/D inputs; pins RB1 and RB4 are multiplexed with EUSART; and pins RB2, RB3, RB6 and RB7 are multiplexed with ECCP. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, RB4:RB0 are configured as analog inputs by default and read as `0'; RB7:RB5 are configured as digital inputs.
TTL Input Buffer
RD TRISB RD LATB Q D EN EN RD PORTB INTx Schmitt Trigger Buffer
To A/D Converter Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>).
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FIGURE 10-8: BLOCK DIAGRAM OF RB1/AN5/TX/CK/INT1 PIN
EUSART Enable
TX/CK Data
1
0
TX/CK TRIS VDD RBPU(2) Analog Input Mode Data Bus WR LATB or PORTB Data Latch D Q CK TRIS Latch D Q CK RB1 pin(1) Weak P Pull-up
WR TRISB
RD TRISB RD LATB Q RD PORTB
TTL Input Buffer
D EN
RD PORTB Schmitt Trigger Input Buffer INT1/CK Input
Analog Input Mode To A/D Converter
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
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FIGURE 10-9: BLOCK DIAGRAM OF RB2/P1B/INT2 PIN
VDD RBPU(2) P Weak Pull-up
P1B Enable P1B Data P1B/D Tri-State Auto-Shutdown 1
0 Data Bus WR LATB or PORTB Data Latch D Q RB2 pin(1) CK TRIS Latch D Q WR TRISB CK
TTL Input Buffer
RD TRISB RD LATB Q RD PORTB EN D
INT2 Input
Schmitt Trigger
RD PORTB
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
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FIGURE 10-10: BLOCK DIAGRAM OF RB3/CCP1/P1A PIN
ECCP1(3) pin Output Enable ECCP1(4) pin Input Enable RBPU(2) P1A/C Tri-State Auto-Shutdown ECCP1/P1A Data Out 1 VDD P 0 RD LATB Data Bus WR LATB or PORTB D CK Q RB3 pin Q N VSS CK Q TTL Input Buffer TRIS Latch Data Latch D WR TRISB Q VDD Weak P Pull-up
RD TRISB Q D EN RD PORTB
ECCP1 Input Schmitt Trigger
Note 1: 2: 3: 4:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). ECCP1 pin output enable active for any PWM mode and Compare mode, where CCP1M<3:0> = 1000 or 1001. ECCP1 pin input enable active for Capture mode only.
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FIGURE 10-11: BLOCK DIAGRAM OF RB4/AN6/RX/DT/KBI0 PIN
EUSART Enabled VDD Analog Input Mode DT TRIS DT Data 1 RBPU(2) P Weak Pull-up
RD LATB Data Bus WR LATB or PORTB D CK Q
0
RB4 pin Q Data Latch D Q Q
WR TRISB
CK
TRIS Latch TTL Input Buffer Q RD PORTB D EN Q1
RD TRISB
Set RBIF
From other RB7:RB4 pins
Q
D RD PORTB EN Schmitt Trigger Q3
RX/DT Input
To A/D Converter
Analog Input Mode
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
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FIGURE 10-12: BLOCK DIAGRAM OF RB5/PGM/KBI1 PIN
VDD RBPU(2) Data Latch D CK TRIS Latch D Q WR TRISB CK TTL Input Buffer Q I/O pin(1) Weak P Pull-up
Data Bus WR LATB or PORTB
ST Buffer
RD TRISB
RD LATB Latch Q RD PORTB EN Set RBIF Q1 D
Q From other RB7:RB5 and RB4 pins RB7:RB5 in Serial Programming Mode Note 1: 2: I/O pins have diode protection to VDD and VSS.
D RD PORTB EN Q3
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
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FIGURE 10-13: BLOCK DIAGRAM OF RB6/PGC/T1OSO/T13CKI/P1C/KBI2 PIN
ECCP1 P1C/D Enable RBPU(2) P1B/D Tri-State Auto-Shutdown P1C Data 1
VDD P Weak Pull-up
0 RD LATB Data Bus WR LATB or PORTB D CK Q Q RB6 pin
Data Latch D WR TRISB CK Q Q Timer1 Oscillator
TRIS Latch From RB7 pin T1OSCEN RD TRISB TTL Buffer Q RD PORTB D EN Q1 Schmitt Trigger
Set RBIF
From other RB7:RB4 pins
Q
D RD PORTB EN Q3
PGC
T13CKI
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
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FIGURE 10-14: BLOCK DIAGRAM OF RB7/PGD/T1OSI/P1D/KBI3 PIN
ECCP1 P1C/D Enable RBPU(2) P1B/D Tri-State Auto-Shutdown P1D Data 1
VDD Weak P Pull-up
To RB6 pin
0 RD LATB Data Bus WR LATB or PORTB D CK Q RB7 pin Q Data Latch D WR TRISB CK Q Q
TRIS Latch
T1OSCEN
RD TRISB
TTL Input Buffer Q D EN
Schmitt Trigger
Set RBIF
RD PORTB
Q1
From other RB7:RB4 pins
Q
D RD PORTB EN Q3
PGD
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
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TABLE 10-3: PORTB FUNCTIONS
Bit# bit 0 bit 1 Buffer TTL(1)/ST(2) TTL(1)/ST(2) Function Input/output port pin, analog input or external interrupt input 0. Input/output port pin, analog input, Enhanced USART Asynchronous Transmit, Addressable USART Synchronous Clock or external interrupt input 1. Input/output port pin or external interrupt input 2. Internal software programmable weak pull-up. Input/output port pin or Capture1 input/Compare1 output/ PWM output. Internal software programmable weak pull-up. Input/output port pin (with interrupt-on-change), analog input, Enhanced USART Asynchronous Receive or Addressable USART Synchronous Data. Input/output port pin (with interrupt-on-change). Internal software programmable weak pull-up. Low-Voltage ICSP enable pin. Name RB0/AN4/INT0 RB1/AN5/TX/CK/INT1
RB2/P1B/INT2 RB3/CCP1/P1A RB4/AN6/RX/DT/KBI0
bit 2 bit 3 bit 4
TTL(1)/ST(2) TTL(1)/ST(3) TTL(1)/ST(4)
RB5/PGM/KBI1
bit 5
TTL(1)/ST(5)
RB6/PGC/T1OSO/T13CKI/ P1C/KBI2
bit 6
TTL(1)/ST(5,6) Input/output port pin (with interrupt-on-change), Timer1/ Timer3 clock input or Timer1oscillator output. Internal software programmable weak pull-up. Serial programming clock. TTL(1)/ST(5) Input/output port pin (with interrupt-on-change) or Timer1 oscillator input. Internal software programmable weak pull-up. Serial programming data.
RB7/PGD/T1OSI/P1D/KBI3
bit 7
Legend: Note 1: 2: 3: 4: 5: 6:
TTL = TTL input, ST = Schmitt Trigger input This buffer is a TTL input when configured as a port input pin. This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when configured as the CCP1 input. This buffer is a Schmitt Trigger input when used as EUSART receive input. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a TTL input when used as the T13CKI input.
TABLE 10-4:
Name PORTB LATB TRISB INTCON INTCON2 INTCON3 ADCON1 Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on POR, BOR xxxq qqqq xxxx xxxx 1111 1111 INT0IE INT2IE PCFG4 RBIE -- INT1IE PCFG3 TMR0IF TMR0IP -- PCFG2 INT0IF -- INT2IF PCFG1 RBIF RBIP INT1IF PCFG0 0000 000x 1111 -1-1 11-0 0-00 -000 0000 Value on all other Resets uuuu uuuu uuuu uuuu 1111 1111 0000 000u 1111 -1-1 11-0 0-00 -000 0000
LATB Data Output Register PORTB Data Direction Register GIE/GIEH PEIE/GIEL TMR0IE RBPU INT2IP -- INT1IP PCFG6 -- PCFG5 INTEDG0 INTEDG1 INTEDG2
x = unknown, u = unchanged, q = value depends on condition. Shaded cells are not used by PORTB.
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11.0 TIMER0 MODULE
The Timer0 module has the following features: * Software selectable as an 8-bit or 16-bit timer/ counter * Readable and writable * Dedicated 8-bit software programmable prescaler * Clock source selectable to be external or internal * Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode * Edge select for external clock Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11-1) is a readable and writable register that controls all the aspects of Timer0, including the prescale selection.
REGISTER 11-1:
T0CON: TIMER0 CONTROL REGISTER
R/W-1 TMR0ON bit 7 R/W-1 T08BIT R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0
bit 7
TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2-0
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FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus RA4/T0CKI pin FOSC/4 0 8 1 1 Programmable Prescaler T0SE 3 T0PS2, T0PS1, T0PS0 T0CS PSA 0 (2 TCY Delay) Set Interrupt Flag bit TMR0IF on Overflow Sync with Internal Clocks TMR0
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
FIGURE 11-2:
RA4/T0CKI pin
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
FOSC/4
0 1 1 Programmable Prescaler 0 Sync with Internal Clocks (2 TCY Delay) TMR0L TMR0 High Byte 8 Set Interrupt Flag bit TMR0IF on Overflow
T0SE 3 T0PS2, T0PS1, T0PS0 T0CS PSA
Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0>
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
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11.1 Timer0 Operation
11.2.1
Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization.
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution).
11.3
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Low-Power Sleep mode, since the timer requires clock cycles even when T0CS is set.
11.4
16-Bit Mode Timer Reads and Writes
11.2
Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, x, ..., etc.) will clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure 11-2). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0, without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. A write to the high byte of Timer0 must also take place through the TMR0H Buffer register. Timer0 high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once.
TABLE 11-1:
Name TMR0L TMR0H INTCON T0CON TRISA Legend: Note 1:
REGISTERS ASSOCIATED WITH TIMER0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx 0000 0000 INT0IE T0SE RBIE PSA TMR0IF T0PS2 INT0IF T0PS1 RBIF T0PS0 0000 000x 1111 1111 11-1 1111 Value on all other Resets uuuu uuuu 0000 0000 0000 000u 1111 1111 11-1 1111
Bit 7
Timer0 Module Low Byte Register Timer0 Module High Byte Register GIE/GIEH TMR0ON RA7
(1)
PEIE/GIEL T08BIT RA6
(1)
TMR0IE T0CS --
PORTA Data Direction Register
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Timer0. RA6 and RA7 are enabled as I/O pins, depending on the oscillator mode selected in Configuration Word 1H.
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NOTES:
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12.0 TIMER1 MODULE
The Timer1 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * Reset from CCP module special event trigger * Status of system clock operation Figure 12-1 is a simplified block diagram of the Timer1 module. Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). The Timer1 oscillator can be used as a secondary clock source in power managed modes. When the T1RUN bit is set, the Timer1 oscillator is providing the system clock. If the Fail-Safe Clock Monitor is enabled and the Timer1 oscillator fails while providing the system clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications, with only a minimal addition of external components and code overhead.
REGISTER 12-1:
T1CON: TIMER1 CONTROL REGISTER
R/W-0 RD16 bit 7 R-0 T1RUN R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations T1RUN: Timer1 System Clock Status bit 1 = System clock is derived from Timer1 oscillator 0 = System clock is derived from another source T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RB6/PGC/T1OSO/T13CKI/P1C/KBI2 (on the rising edge) 0 = Internal clock (Fosc/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
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12.1 Timer1 Operation
Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input, or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/T1OSO/ T13CKI/P1C/KBI2 pins become inputs. That is, the TRISB7:TRISB6 values are ignored and the pins read as `0'. Timer1 also has an internal "Reset input". This Reset can be generated by the CCP module (see Section 15.4.4 "Special Event Trigger").
FIGURE 12-1:
TMR1IF Overflow Interrupt Flag bit
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger TMR1 TMR1H CLR TMR1L
1 0
Synchronized Clock Input
TMR1ON On/Off T13CKI/T1OSO T1OSI T1OSC T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock
1
T1SYNC Prescaler 1, 2, 4, 8 Synchronize det Peripheral Clocks
0
2 T1CKPS1:T1CKPS0 TMR1CS
Note 1:
When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
8
TMR1H
Data Bus<7:0>
8 Write TMR1L Read TMR1L TMR1IF Overflow Interrupt Flag bit 8 Timer 1 High Byte TMR1
8 CCP Special Event Trigger
0
CLR TMR1L
1
Synchronized Clock Input
T1OSC T13CKI/T1OSO T1OSCEN Enable Oscillator(1)
TMR1ON on/off
1
T1SYNC Prescaler 1, 2, 4, 8 Synchronize det
T1OSI
FOSC/4 Internal Clock
0
2 TMR1CS T1CKPS1:T1CKPS0 Peripheral Clocks
Note 1:
When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
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12.2 Timer1 Oscillator
FIGURE 12-3:
A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated for 32 kHz crystals. It will continue to run during all power managed modes. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. Note: The Timer1 oscillator shares the T1OSI and T1OSO pins with the PGD and PGC pins used for programming and debugging. When using the Timer1 oscillator, In-Circuit Serial Programming (ICSP) may not function correctly (high voltage or low voltage), or the In-Circuit Debugger (ICD) may not communicate with the controller. As a result of using either ICSP or ICD, the Timer1 crystal may be damaged. If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead), or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation. Note:
EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR
PGD
C1 22 pF
PIC18FXXXX
PGD/T1OSI
XTAL 32.768 kHz PGC/T1OSO C2 22 pF PGC
See the Notes with Table 12-1 for additional information about capacitor selection.
TABLE 12-1:
Osc Type LP
CAPACITOR SELECTION FOR THE TIMER OSCILLATOR
Freq 32 kHz 22 C1 pF(1) C2 22 pF(1)
Note 1: Microchip suggests this value as a starting point in validating the oscillator circuit. Oscillator operation should then be tested to ensure expected performance under all expected conditions (VDD and temperature). 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only.
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12.3 Timer1 Oscillator Layout Considerations 12.5 Resetting Timer1 Using a CCP Trigger Output
The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in output compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 12-4, may be helpful when used on a single sided PCB, or in addition to a ground plane.
If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion, if the A/D module is enabled (see Section 15.4.4 "Special Event Trigger" for more information). Note: The special event triggers from the CCP1 module will not set interrupt flag bit, TMR1IF (PIR1<0>).
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1.
FIGURE 12-4:
OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING
RB2
RA1
RA4 MCLR
OSC1 OSC2
C2 X1 C3
12.6
Timer1 16-Bit Read/Write Mode
VSS
VDD
C1
RA2 RA3
RB7 RB6
C4 X2 C5
Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid, due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L.
RB0
RB5
Note: Not drawn to scale.
12.4
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>).
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12.7 Using Timer1 as a Real-Time Clock
Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it; the simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times.
Adding an external LP oscillator to Timer1 (such as the one described in Section 12.2 "Timer1 Oscillator", above), gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow, triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow.
EXAMPLE 12-1:
RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN RTCisr BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
0x80 TMR1H TMR1L b'00001111' T1OSC secs mins .12 hours PIE1, TMR1IE ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ;
; Enable Timer1 interrupt
TMR1H, 7 PIR1, TMR1IF secs, F .59 secs secs mins, F .59 mins mins hours, F .23 hours .01 hours
; ; ; ; ; ; ; ; ; ; ; ;
Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? No, done Clear seconds Increment minutes 60 minutes elapsed? No, done clear minutes Increment hours 24 hours elapsed?
; No, done ; Reset hours to 1 ; Done
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TABLE 12-2:
Name INTCON PIR1 PIE1 IPR1 TMR1L TMR1H T1CON Legend: Bit 7
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE -- -- -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other Resets
GIE/GIEH PEIE/GIEL -- -- -- ADIF ADIE ADIP
0000 000x 0000 000u -000 -000 -000 -000 -000 -000 -000 -000 -111 -111 -111 -111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register RD16 T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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13.0
* * * * * *
TIMER2 MODULE
13.1
Timer2 Operation
The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match with PR2
Timer2 has a control register shown in Register 13-1. TMR2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. Figure 13-1 is a simplified block diagram of the Timer2 module. Register 13-1 shows the Timer2 Control register. The prescaler and postscaler selection of Timer2 are controlled by this register.
Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written.
REGISTER 13-1:
T2CON: TIMER2 CONTROL REGISTER
U-0 -- bit 7 R/W-0 TOUTPS3 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 R/W-0 R/W-0 T2CKPS0 bit 0 TMR2ON T2CKPS1
bit 7 bit 6-3
Unimplemented: Read as `0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 2
bit 1-0
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13.2 Timer2 Interrupt 13.3 Output of TMR2
The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate the shift clock.
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
TMR2 Output(1) Sets Flag bit TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16 2 T2CKPS1:T2CKPS0
TMR2
Reset
Comparator EQ PR2
Postscaler 1:1 to 1:16 4
TOUTPS3:TOUTPS0
TABLE 13-1:
Name Bit 7
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE -- -- -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other Resets
INTCON GIE/GIEH PEIE/GIEL PIR1 PIE1 IPR1 TMR2 T2CON PR2 Legend: -- -- -- -- ADIF ADIE ADIP
0000 000x 0000 000u -000 -000 -000 -000 -000 -000 -000 -000 -111 -111 -111 -111 0000 0000 0000 0000
Timer2 Module Register Timer2 Period Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module.
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14.0 TIMER3 MODULE
Figure 14-1 is a simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. Register 12-1 shows the Timer1 Control register. This register controls the operating mode of the Timer1 module, as well as contains the Timer1 Oscillator Enable bit (T1OSCEN), which can be a clock source for Timer3. The Timer3 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers; TMR3H and TMR3L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * Reset from CCP module trigger
REGISTER 14-1:
T3CON: TIMER3 CONTROL REGISTER
R/W-0 RD16 bit 7 U-0 -- R/W-0 T3CKPS1 R/W-0 T3CKPS0 R/W-0 T3CCP1 R/W-0 T3SYNC R/W-0 TMR3CS R/W-0 TMR3ON bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations Unimplemented: Read as `0' T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T3CCP1: Timer3 and Timer1 to CCP1 Enable bits 1 = Timer3 is the clock source for compare/capture CCP module 0 = Timer1 is the clock source for compare/capture CCP module T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6 bit 5-4
bit 3
bit 2
bit 1
bit 0
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14.1 Timer3 Operation
Timer3 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/PGC/ T1OSO/T13CKI/P1C/KBI2 pins become inputs. That is, the TRISB7:TRISB6 value is ignored and the pins are read as `0'. Timer3 also has an internal "Reset input". This Reset can be generated by the CCP module (see Section 15.4.4 "Special Event Trigger").
FIGURE 14-1:
TMR3IF Overflow Interrupt Flag bit
TIMER3 BLOCK DIAGRAM
CCP Special Event Trigger T3CCPx CLR TMR3H TMR3L
1 0
Synchronized Clock Input
TMR3ON On/Off T1OSO/ T13CKI T1OSC
1
T3SYNC
T1OSI
T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock
Prescaler 1, 2, 4, 8
0
Synchronize det
2 TMR3CS T3CKPS1:T3CKPS0 Peripheral Clocks
Note 1:
When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
8 TMR3H 8 8
Data Bus<7:0>
Write TMR3L Read TMR3L Set TMR3IF Flag bit on Overflow 8 Timer3 High Byte TMR3 TMR3L CLR
1
CCP Special Event Trigger T3CCPx Synchronized
0
Clock Input
To Timer1 Clock Input T1OSO/ T13CKI T1OSC
TMR3ON On/Off
1
T3SYNC Prescaler 1, 2, 4, 8 Synchronize det Peripheral Clocks
T1OSI
T1OSCEN Enable Oscillator(1)
FOSC/4 Internal Clock
0
2 T3CKPS1:T3CKPS0 TMR3CS
Note 1:
When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
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14.2 Timer1 Oscillator 14.4
The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a lowpower oscillator rated for 32 kHz crystals. See Section 12.2 "Timer1 Oscillator" for further details.
Resetting Timer3 Using a CCP Trigger Output
If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. See Section 15.4.4 "Special Event Trigger" for more information. Note: The special event triggers from the CCP module will not set interrupt flag bit, TMR3IF (PIR1<0>).
14.3
Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR3 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled/disabled by setting/clearing TMR3 Interrupt Enable bit, TMR3IE (PIE2<1>).
Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer3 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer3 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer3.
TABLE 14-1:
Name INTCON PIR2 PIE2 IPR2 TMR3L TMR3H T1CON T3CON Legend: Bit 7 GIE/ GIEH
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Bit 6 PEIE/ GIEL -- -- -- Bit 5 TMR0IE -- -- -- Bit 4 INT0IE EEIF EEIE EEIP Bit 3 RBIE -- -- -- Bit 2 TMR0IF LVDIF LVDIE LVDIP Bit 1 INT0IF TMR3IF TMR3IE TMR3IP Bit 0 RBIF -- -- -- Value on POR, BOR Value on all other Resets
0000 000x 0000 000u 0--0 -00- 0--0 -000--0 -00- 0--0 -001--1 -11- 1--1 -11xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
OSCFIF OSCFIE OSCFIP
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register Holding Register for the Most Significant Byte of the 16-bit TMR3 Register RD16 RD16 T1RUN -- T1CKPS1 T1CKPS0 T1OSCEN T3CKPS1 T3CKPS0 T3CCP1 T1SYNC T3SYNC
TMR1CS TMR1ON 0000 0000 u0uu uuuu TMR3CS TMR3ON 0-00 0000 u-uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer3 module.
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NOTES:
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15.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE
The control register for CCP1 is shown in Register 15-1. In addition to the expanded functions of the CCP1CON register, the ECCP module has two additional registers associated with Enhanced PWM operation and auto-shutdown features: * PWM1CON * ECCPAS
The Enhanced CCP module is implemented as a standard CCP module with Enhanced PWM capabilities. These capabilities allow for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown and restart and are discussed in detail in Section 15.5 "Enhanced PWM Mode".
REGISTER 15-1:
CCP1CON REGISTER FOR ENHANCED CCP OPERATION
R/W-0 P1M1 bit 7 R/W-0 P1M0 R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0
bit 7-6
P1M1:P1M0: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive DC1B1:DC1B0: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. CCP1M3:CCP1M0: ECCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (ECCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (ECCP1IF bit is set) 1001 = Compare mode, clear output on match (ECCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (ECCP1IF bit is set, ECCP1 pin returns to port pin operation) 1011 = Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1 or TMR3 and starts an A/D conversion if the A/D module is enabled) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend: R = Readable bit -n = Value at POR
bit 5-4
bit 3-0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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15.1 ECCP Outputs
The Enhanced CCP module may have up to four outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTB. The pin assignments are summarized in Table 15-1. To configure I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1Mn and CCP1Mn bits (CCP1CON<7:6> and <3:0>, respectively). The appropriate TRISB direction bits for the port pins must also be set as outputs.
TABLE 15-1:
ECCP Mode Compatible CCP Dual PWM Quad PWM Legend: Note 1:
PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
CCP1CON Configuration 00xx 11xx 10xx 11xx x1xx 11xx RB3 CCP1 P1A P1A RB2 RB2/INT2 P1B P1B RB6 RB6/PGC/T1OSO/T13CKI/KBI2 RB6/PGC/T1OSO/T13CKI/KBI2 P1C RB7 RB7/PGD/T1OSI/KBI3 RB7/PGD/T1OSI/KBI3 P1D
x = Don't care. Shaded cells indicate pin assignments not used by ECCP in a given mode. TRIS register values must be configured appropriately.
15.2
CCP Module
15.3.1
CCP PIN CONFIGURATION
Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable.
In Capture mode, the RB3/CCP1/P1A pin should be configured as an input by setting the TRISB<3> bit. Note: If the RB3/CCP1/P1A is configured as an output, a write to the port can cause a capture condition.
TABLE 15-2:
CCP MODE - TIMER RESOURCE
Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2
15.3.2
TIMER1/TIMER3 MODE SELECTION
CCP Mode Capture Compare PWM
15.3
Capture Mode
The timers that are to be used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with the CCP module is selected in the T3CON register.
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RB3/CCP1/P1A. An event is defined as one of the following: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge
15.3.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit, CCP1IE (PIE1<2>), clear while changing capture modes to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode.
The event is selected by control bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<2>), is set; it must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value.
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15.3.4 CCP PRESCALER
There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 15-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
EXAMPLE 15-1:
CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
; ; ; ; ; ; Turn CCP module off Load WREG with the new prescaler mode value and CCP ON Load CCP1CON with this value
CCP1CON NEW_CAPT_PS
MOVWF
CCP1CON
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H Set Flag bit CCP1IF Prescaler / 1, 4, 16 T3CCP1 TMR3 Enable CCPR1H and Edge Detect CCP1CON<3:0> Q's TMR1 Enable TMR1H TMR1L CCPR1L TMR3L
CCP1 pin
T3CCP1
15.4
Compare Mode
15.4.2
TIMER1/TIMER3 MODE SELECTION
In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the RB3/CCP1/P1A pin: * * * * Is driven high Is driven low Toggles output (high-to-low or low-to-high) Remains unchanged (interrupt only)
Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
15.4.3
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the RB3/ CCP1/P1A pin is not affected. CCP1IF is set and an interrupt is generated (if enabled).
The action on the pin is based on the value of control bits, CCP1M3:CCP1M0. At the same time, interrupt flag bit, CCP1IF, is set.
15.4.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special event trigger also sets the GO/DONE bit (ADCON0<1>). This starts a conversion of the currently selected A/D channel if the A/D is on.
15.4.1
CCP PIN CONFIGURATION
The user must configure the RB3/CCP1/P1A pin as an output by clearing the TRISB<3> bit. Note: Clearing the CCP1CON register will force the RB3/CCP1/P1A compare output latch to the default low level. This is not the PORTB I/O data latch.
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FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will: Reset Timer1 or Timer3, but does not set Timer1 or Timer3 interrupt flag bit and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion.
Special Event Trigger Set Flag bit CCP1IF CCPR1H CCPR1L Q RB3/CCP1/P1A pin TRISB<3> Output Enable S R Output Logic Comparator
Match T3CCP1
CCP1CON<3:0> Mode Select
0
1
TMR1H
TMR1L
TMR3H
TMR3L
TABLE 15-3:
Name INTCON PIR1 PIE1 IPR1 TRISB TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON TMR3L TMR3H T3CON ADCON0 Legend:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE -- -- -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF Value on POR, BOR Value on all other Resets
Bit 7
GIE/GIEH PEIE/GIEL -- -- -- ADIF ADIE ADIP
0000 000x 0000 000u
TMR1IF -000 -000 -000 -000 TMR1IE -000 -000 -000 -000 TMR1IP -111 -111 -111 -111 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
PORTB Data Direction Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 Holding Register for the Least Significant Byte of the 16-bit TMR3 Register Holding Register for the Most Significant Byte of the 16-bit TMR3 Register RD16 VCFG1 -- VCFG0 T3CKPS1 T3CKPS0 -- CHS2 T3CCP1 CHS1 T3SYNC CHS0
TMR1CS TMR1ON 0000 0000 uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
TMR3CS TMR3ON 0-00 0000 u-uu uuuu GO/DONE ADON 00-0 0000 00-0 0000
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by Capture and Timer1.
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15.5 Enhanced PWM Mode
15.5.2 PWM DUTY CYCLE
The Enhanced PWM Mode provides additional PWM output options for a broader range of control applications. The module is an upwardly compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low). The module's output mode and polarity are configured by setting the P1M1:P1M0 and CCP1M3CCP1M0 bits of the CCP1CON register (CCP1CON<7:6> and CCP1CON<3:0>, respectively). Figure 15-3 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is the PWM Delay register, ECCP1DEL, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). Because of the buffering, the module waits until the assigned timer resets instead of starting immediately. This means that Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle (4 TOSC). As before, the user must manually configure the appropriate TRIS bits for output. The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the equation:
EQUATION 15-2:
PWM DUTY CYCLE
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation:
15.5.1
PWM PERIOD
EQUATION 15-3:
PWM RESOLUTION
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the equation:
log FOSC FPWM PWM Resolution (max) = log(2)
(
) bits
EQUATION 15-1:
PWM PERIOD
PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is copied from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 13.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
Note:
If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.
15.5.3
PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: * * * * Single Output Half-Bridge Output Full-Bridge Output, Forward mode Full-Bridge Output, Reverse mode
The Single Output mode is the Standard PWM mode discussed in Section 15.5 "Enhanced PWM Mode". The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 15-4.
TABLE 15-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
2.44 kHz 16 FFh 10 9.77 kHz 4 FFh 10 39.06 kHz 1 FFh 10 156.25 kHz 1 3Fh 8 312.50 kHz 1 1Fh 7 416.67 kHz 1 17h 6.58
PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
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FIGURE 15-3:
Duty Cycle Registers CCPR1L CCP1/P1A TRISB<3> CCPR1H (Slave) P1B R Q Output Controller P1C TMR2 (Note 1) S P1D Clear Timer, set CCP1 pin and latch D.C. CCP1DEL TRISB<7> TRISB<6> RB7/PGD/T1OSI/P1D/KBI3 TRISB<2> RB6/PGC/T1OSO/T13CKI/ P1C/KBI2 RB2/P1B/INT2 RB3/CCP1/P1A
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4> P1M1<1:0> 2 CCP1M<3:0> 4
Comparator
Comparator
PR2
Note:
The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base.
FIGURE 15-4:
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
0 SIGNAL Duty Cycle Period PR2+1
CCP1CON<7:6>
00
(Single Output)
P1A Modulated Delay(1) P1A Modulated Delay(1)
10
(Half-Bridge)
P1B Modulated P1A Active
01
(Full-Bridge, Forward)
P1B Inactive P1C Inactive P1D Modulated P1A Inactive
11
(Full-Bridge, Reverse)
P1B Modulated P1C Active P1D Inactive
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FIGURE 15-5: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0 CCP1CON<7:6> SIGNAL Duty Cycle Period 00 (Single Output) P1A Modulated P1A Modulated 10 (Half-Bridge) Delay(1) P1B Modulated P1A Active (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Delay(1) PR2+1
01
11
Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section 15.5.6 "Programmable Dead-Band Delay").
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15.5.4 HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the RB3/CCP1/P1A pin, while the complementary PWM output signal is output on the RB2/P1B/INT2 pin (Figure 15-6). This mode can be used for half-bridge applications, as shown in Figure 15-7, or for full-bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge Output mode, the programmable deadband delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits, PDC6:PDC0 (PWM1CON<6:0>), sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 15.5.6 "Programmable Dead-Band Delay" for more details of the dead-band delay operations. The TRISB<3> and TRISB<2> bits must be cleared to configure P1A and P1B as outputs.
FIGURE 15-6:
Period Duty Cycle P1A td
HALF-BRIDGE PWM OUTPUT (ACTIVE-HIGH)
Period
td P1B
(1) (1) (1)
td = Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register.
FIGURE 15-7:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
Standard Half-Bridge Circuit ("Push-Pull") PIC18F1220/1320 P1A FET Driver
+ V Load
FET Driver P1B
+ V -
Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F1220/1320 FET Driver P1A Load FET Driver
FET Driver P1B
FET Driver
V-
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15.5.5 FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin RB3/CCP1/P1A is continuously active and pin RB7/PGD/T1OSI/P1D/KBI3 is modulated. In the Reverse mode, pin RB6/PGC/ T1OSO/T13CKI/P1C/KBI2 is continuously active and pin RB2/P1B/INT2 is modulated. These are illustrated in Figure 15-8. The TRISB<3:2> and TRISB<7:6> bits must be cleared to make the P1A, P1B, P1C and P1D pins output.
FIGURE 15-8:
Forward Mode
FULL-BRIDGE PWM OUTPUT (ACTIVE-HIGH)
Period P1A Duty Cycle P1B
P1C
P1D (1) Reverse Mode Period Duty Cycle P1A (1)
P1B P1C
P1D (1) (1)
Note 1:
At this time, the TMR2 register is equal to the PR2 register.
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FIGURE 15-9: EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F1220/1320 P1A
FET Driver
QA
QC
FET Driver
P1B FET Driver
Load FET Driver
P1C
QB
QD
VP1D
15.5.5.1
Direction Change in Full-Bridge Mode
In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the Forward/Reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle. Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive state, while the unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. This occurs in a time interval of (4 TOSC * (Timer2 Prescale Value) before the next PWM period begins. The Timer2 prescaler will be either 1,4 or 16, depending on the value of the T2CKPS bit (T2CON<1:0>). During the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (P1B and P1D) remain inactive. This relationship is shown in Figure 15-10. Note that in the Full-Bridge Output mode, the ECCP module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time.
Figure 15-11 shows an example where the PWM direction changes from forward to reverse, at a near 100% duty cycle. At time t1, the output P1A and P1D become inactive, while output P1C becomes active. In this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices QC and QD (see Figure 15-9) for the duration of `t'. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. 2. Reduce PWM for a PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on.
Other options to prevent shoot-through current may exist.
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FIGURE 15-10:
SIGNAL
PWM DIRECTION CHANGE (ACTIVE-HIGH)
PWM Period(1) PWM Period
P1A P1B DC P1C P1D DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C toggle one Timer2 count before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. One Timer2 Count(2)
FIGURE 15-11:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE (ACTIVE-HIGH)
Forward Period t1 Reverse Period
P1A P1B P1C P1D DC
DC tON
External Switch C tOFF External Switch D Potential Shoot-Through Current t = tOFF - tON
Note 1:
tON is the turn-on delay of power switch QC and its driver.
2: tOFF is the turn-off delay of power switch QD and its driver.
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15.5.6 PROGRAMMABLE DEAD-BAND DELAY
In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shootthrough current) may flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 15-6 for an illustration. The lower seven bits of the PWM1CON register (Register 15-2) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). A shutdown event can be caused by the INT0, INT1 or INT2 pins (or any combination of these three sources). The auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. The autoshutdown sources to be used are selected using the ECCPAS2:ECCPAS0 bits (bits <6:4> of the ECCPAS register). When a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits (ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/P1D) may be set to drive high, drive low or be tristated (not driving). The ECCPASE bit (ECCPAS<7>) is also set to hold the Enhanced PWM outputs in their shutdown states. The ECCPASE bit is set by hardware when a shutdown event occurs. If automatic restarts are not enabled, the ECCPASE bit is cleared by firmware when the cause of the shutdown clears. If automatic restarts are enabled, the ECCPASE bit is automatically cleared when the cause of the auto-shutdown has cleared. If the ECCPASE bit is set when a PWM period begins, the PWM outputs remain in their shutdown state for that entire PWM period. When the ECCPASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active.
15.5.7
ENHANCED PWM AUTO-SHUTDOWN
When the ECCP is programmed for any of the Enhanced PWM modes, the active output pins may be configured for auto-shutdown. Auto-shutdown immediately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs.
REGISTER 15-2:
PWM1CON: PWM CONFIGURATION REGISTER
R/W-0 PRSEN bit 7 R/W-0 PDC6 R/W-0 PDC5 R/W-0 PDC4 R/W-0 PDC3 R/W-0 PDC2 R/W-0 PDC1 R/W-0 PDC0 bit 0
bit 7
PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM PDC<6:0>: PWM Delay Count bits Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-0
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REGISTER 15-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM/AUTO-SHUTDOWN CONTROL REGISTER
R/W-0 bit 7 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state ECCPAS2: ECCP Auto-Shutdown bit 2 0 = INT0 pin has no effect 1 = INT0 pin low causes shutdown ECCPAS1: ECCP Auto-Shutdown bit 1 0 = INT2 pin has no effect 1 = INT2 pin low causes shutdown ECCPAS0: ECCP Auto-Shutdown bit 0 0 = INT1 pin has no effect 1 = INT1 pin low causes shutdown PSSACn: Pins A and C Shutdown State Control bits 00 = Drive Pins A and C to `0' 01 = Drive Pins A and C to `1' 1x = Pins A and C tri-state PSSBDn: Pins B and D Shutdown State Control bits 00 = Drive Pins B and D to `0' 01 = Drive Pins B and D to `1' 1x = Pins B and D tri-state Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 PSSAC1 R/W-0 PSSAC0 R/W-0 PSSBD1 R/W-0 PSSBD0 bit 0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
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15.5.7.1 Auto-Shutdown and Automatic Restart 15.5.8 START-UP CONSIDERATIONS
The auto-shutdown feature can be configured to allow automatic restarts of the module, following a shutdown event. This is enabled by setting the PRSEN bit of the PWM1CON register (PWM1CON<7>). In Shutdown mode with PRSEN = 1 (Figure 15-12), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is automatically cleared. If PRSEN = 0 (Figure 15-13), once a shutdown condition occurs, the ECCPASE bit will remain set until it is cleared by firmware. Once ECCPASE is cleared, the Enhanced PWM will resume at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. When the ECCP module is used in the PWM mode, the application hardware must use the proper external pullup and/or pull-down resistors on the PWM output pins. When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the off state, until the microcontroller drives the I/O pins with the proper signal levels, or activates the PWM output(s). The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended, since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP module may cause damage to the application circuit. The ECCP module must be enabled in the proper output mode and complete a full PWM cycle, before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins.
Independent of the PRSEN bit setting, the ECCPASE bit cannot be cleared as long as the cause of the shutdown persists. The Auto-Shutdown mode can be forced by writing a `1' to the ECCPASE bit.
FIGURE 15-12:
PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
PWM Period PWM Period PWM Period
PWM Activity Dead Time Duty Cycle Shutdown Event Dead Time Duty Cycle Dead Time Duty Cycle
ECCPASE bit
FIGURE 15-13:
PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
PWM Period PWM Period PWM Period
PWM Activity Dead Time Duty Cycle Shutdown Event Dead Time Duty Cycle Dead Time Duty Cycle
ECCPASE bit ECCPASE Cleared by Firmware
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15.5.9 SETUP FOR PWM OPERATION 15.5.10
The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. Configure the PWM pins P1A and P1B (and P1C and P1D, if used) as inputs by setting the corresponding TRISB bits. Set the PWM period by loading the PR2 register. Configure the ECCP module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: * Select one of the available output configurations and direction with the P1M1:P1M0 bits. * Select the polarities of the PWM output signals with the CCP1M3:CCP1M0 bits. Set the PWM duty cycle by loading the CCPR1L register and CCP1CON<5:4> bits. For Half-Bridge Output mode, set the deadband delay by loading PWM1CON<6:0> with the appropriate value. If auto-shutdown operation is required, load the ECCPAS register: * Select the auto-shutdown sources using the ECCPAS<2:0> bits. * Select the shutdown states of the PWM output pins using PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits. * Set the ECCPASE bit (ECCPAS<7>). If auto-restart operation is required, set the PRSEN bit (PWM1CON<7>). Configure and start TMR2: * Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). * Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). * Enable Timer2 by setting the TMR2ON bit (T2CON<2>). Enable PWM outputs after a new PWM cycle has started: * Wait until TMR2 overflows (TMR2IF bit is set). * Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRISB bits. * Clear the ECCPASE bit (ECCPAS<7>).
OPERATION IN LOW-POWER MODES
2. 3.
In the Low-Power Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCP pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If TwoSpeed Start-ups are enabled, the initial start-up frequency may not be stable if the INTOSC is being used. In PRI_IDLE mode, the primary clock will continue to clock the ECCP module without change. In all other low-power modes, the selected low-power mode clock will clock Timer2. Other low-power mode clocks will most likely be different than the primary clock frequency.
4. 5.
15.5.10.1
Operation with Fail-Safe Clock Monitor
6.
If the Fail-Safe Clock Monitor is enabled (CONFIG1H<6> is programmed), a clock failure will force the device into the Low-Power RC_RUN mode and the OSCFIF bit (PIR2<7>) will be set. The ECCP will then be clocked from the INTRC clock source, which may have a different clock frequency than the primary clock. By loading the IRCF2:IRCF0 bits on Resets, the user can enable the INTOSC at a high clock speed in the event of a clock failure. See the previous section for additional details.
7. 8.
15.5.11
EFFECTS OF A RESET
Both power-on and subsequent Resets will force all ports to input mode and the CCP registers to their Reset states. This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module.
9.
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TABLE 15-5:
Name INTCON RCON PIR1 PIE1 IPR1 TMR2 PR2 T2CON TRISB CCPR1H CCPR1L CCP1CON ECCPAS PWM1CON OSCCON Legend:
REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Bit 6 Bit 5 TMR0IE -- RCIF RCIE RCIP Bit 4 INT0IE RI TXIF TXIE TXIP Bit 3 RBIE TO -- -- -- Bit 2 TMR0IF PD CCP1IF CCP1IE CCP1IP Bit 1 INT0IF POR TMR2IF TMR2IE TMR2IP Bit 0 RBIF BOR TMR1IF Value on POR, BOR Value on all other Resets
Bit 7
GIE/GIEH PEIE/GIEL IPEN -- -- -- -- ADIF ADIE ADIP
0000 000x 0000 000u 0--1 11qq 0--q qquu -000 -000 -000 -000
TMR1IE -000 -000 -000 -000 TMR1IP -111 -111 -111 -111 0000 0000 0000 0000 1111 1111 1111 1111
Timer2 Module Register Timer2 Module Period Register -- TOUTPS3 PORTB Data Direction Register Enhanced Capture/Compare/PWM Register 1 High Byte Enhanced Capture/Compare/PWM Register 1 Low Byte P1M1 PRSEN IDLEN P1M0 PDC6 IRCF2 DC1B1 PDC5 IRCF1 DC1B0 PDC4 IRCF0 CCP1M3 PDC3 OSTS CCP1M2 PSSAC0 PDC2 IOFS CCP1M1 PSSBD1 PDC1 SCS1 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1
TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M0 0000 0000 0000 0000 PSSBD0 0000 0000 0000 0000 PDC0 SCS0 0000 0000 uuuu uuuu 0000 qq00 0000 qq00
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the ECCP module in Enhanced PWM mode.
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16.0 ENHANCED ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART)
16.1 Asynchronous Operation in Power Managed Modes
The Enhanced Addressable Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced Addressable USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These features make it ideally suited for use in Local Interconnect Network (LIN) bus systems. The EUSART can be configured in the following modes: * Asynchronous (full duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission * Synchronous - Master (half duplex) with selectable clock polarity * Synchronous - Slave (half duplex) with selectable clock polarity The RB1/AN5/TX/CK/INT1 and RB4/AN6/RX/DT/KBI0 pins must be configured as follows for use with the Universal Synchronous Asynchronous Receiver Transmitter: * * * * SPEN (RCSTA<7>) bit must be set ( = 1), PCFG6:PCFG5 (ADCON1<5:6>) must be set ( = 1), TRISB<4> bit must be set ( = 1) and TRISB<1> bit must be set ( = 1). Note: The EUSART control will automatically reconfigure the pin from input to output as needed.
The EUSART may operate in Asynchronous mode while the peripheral clocks are being provided by the internal oscillator block. This makes it possible to remove the crystal or resonator that is commonly connected as the primary clock on the OSC1 and OSC2 pins. The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz (see Table 22-6). However, this frequency may drift as VDD or temperature changes and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output back to 8 MHz. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source (see Section 3.6 "INTOSC Frequency Drift" for more information). The other method adjusts the value in the Baud Rate Generator (BRG). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.
The operation of the Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCTL) These are detailed in on the following pages in Register 16-1, Register 16-2 and Register 16-3, respectively.
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REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 CSRC bit 7 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: bit 4 SREN/CREN overrides TXEN in Sync mode. R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 SENDB R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
bit 6
bit 5
SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care. BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. TRMT: Transmit Shift Register Status bit 1 = TSR Idle 0 = TSR busy TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3
bit 2
bit 1
bit 0
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REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, generates RCIF interrupt and loads RCREG when RX9D is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care. FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 16-3: BAUDCTL: BAUD RATE CONTROL REGISTER
U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as `0' RCIDL: Receive Operation Idle Status bit 1 = Receiver is Idle 0 = Receiver is busy Unimplemented: Read as `0' SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator - SPBRG only (Compatible mode), SPBRGH value ignored Unimplemented: Read as `0' WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character - requires reception of a Sync byte (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-1 RCIDL U-0 -- R/W-0 SCKP R/W-0 BRG16 U-0 -- R/W-0 WUE R/W-0 ABDEN bit 0
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
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16.2 EUSART Baud Rate Generator (BRG)
16.2.1 POWER MANAGED MODE OPERATION
The system clock is used to generate the desired baud rate; however, when a power managed mode is entered, the clock source may be operating at a different frequency than in PRI_RUN mode. In Sleep mode, no clocks are present and in PRI_IDLE mode, the primary clock source continues to provide clocks to the Baud Rate Generator; however, in other power managed modes, the clock frequency will probably change. This may require the value in SPBRG to be adjusted. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit and make sure that the receive operation is Idle before changing the system clock.
The BRG is a dedicated 8-bit or 16-bit generator, that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCTL<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 also control the baud rate. In Synchronous mode, bit BRGH is ignored. Table 16-1 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table 16-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 16-1. Typical baud rates and error values for the various asynchronous modes are shown in Table 16-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
16.2.2
SAMPLING
The data on the RB4/AN6/RX/DT/KBI0 pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
TABLE 16-1:
SYNC 0 0 0 0 1 1
BAUD RATE FORMULAS
BRG/EUSART Mode BRG16 0 0 1 1 0 1 BRGH 0 1 0 1 x x 8-bit/Asynchronous 8-bit/Asynchronous 16-bit/Asynchronous 16-bit/Asynchronous 8-bit/Synchronous 16-bit/Synchronous FOSC/[4 (n + 1)] FOSC/[64 (n + 1)] FOSC/[16 (n + 1)] Baud Rate Formula
Configuration Bits
Legend: x = Don't care, n = value of SPBRGH:SPBRG register pair
EXAMPLE 16-1:
CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16%
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TABLE 16-2:
Name TXSTA RCSTA BAUDCTL SPBRGH SPBRG Legend:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 6 TX9 RX9 RCIDL Bit 5 TXEN SREN -- Bit 4 SYNC CREN SCKP Bit 3 SENDB ADDEN BRG16 Bit 2 BRGH FERR -- Bit 1 TRMT OERR WUE Bit 0 TX9D RX9D ABDEN Value on POR, BOR 0000 -010 0000 -00x -1-1 0-00 0000 0000 0000 0000 Value on all other Resets 0000 -010 0000 -00x -1-1 0-00 0000 0000 0000 0000
Bit 7 CSRC SPEN --
Baud Rate Generator Register High Byte Baud Rate Generator Register Low Byte x = unknown, - = unimplemented, read as `0'. Shaded cells are not used by the BRG.
TABLE 16-3:
BAUD RATE (K)
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz Actual Rate (K) -- 1.221 2.404 9.766 19.531 62.500 104.167 % Error -- 1.73 0.16 1.73 1.73 8.51 -9.58 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) -- 1.202 2.404 9.766 19.531 52.083 78.125 % Error -- 0.16 0.16 1.73 1.73 -9.58 -32.18 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) -- 1201 2403 9615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2 BAUD RATE (K)
-- -- 255 64 31 10 4
-- 255 129 31 15 4 2
-- 129 64 15 7 2 1
-- 103 51 12 -- -- --
SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 8.929 20.833 62.500 62.500 % Error 0.16 0.16 0.16 -6.99 8.51 8.51 -45.75 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 300 1201 2403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 300 1201 -- -- -- -- -- % Error -0.16 -0.16 -- -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
207 51 25 6 2 0 0
103 25 12 -- -- -- --
51 12 -- -- -- -- --
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TABLE 16-3:
BAUD RATE (K)
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 20.000 MHz Actual Rate (K) -- 9.615 19.231 56.818 113.636 % Error -- 0.16 0.16 -1.36 -1.36 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) -- 9.766 19.231 58.140 113.636 % Error -- 1.73 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 2.441 9.615 19.531 56.818 125.000 % Error 1.73 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) 2403 9615 19230 55555 -- % Error -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
2.4 9.6 19.2 57.6 115.2 BAUD RATE (K)
-- 255 129 42 21
-- 129 64 21 10
255 64 31 10 4
207 51 25 8 --
SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 4.000 MHz Actual Rate (K) -- 1.202 2.404 9.615 19.231 62.500 125.000 % Error -- 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) -- 1201 2403 9615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 300 1201 2403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
-- 207 103 25 12 3 1
-- 103 51 12 -- -- --
207 51 25 -- -- -- --
SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.399 9.615 19.231 56.818 113.636 % Error 0.02 -0.03 -0.03 0.16 0.16 -1.36 -1.36 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.531 56.818 125.000 % Error 0.02 -0.03 0.16 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) 300 1201 2403 9615 19230 55555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2 BAUD RATE (K)
8332 2082 1040 259 129 42 21
4165 1041 520 129 64 21 10
2082 520 259 64 31 10 4
1665 415 207 51 25 8 --
SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 9.615 19.231 62.500 125.000 % Error 0.04 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 300 1201 2403 9615 -- -- -- % Error -0.16 -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 300 1201 2403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
832 207 103 25 12 3 1
415 103 51 12 -- -- --
207 51 25 -- -- -- --
(c) 2007 Microchip Technology Inc.
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TABLE 16-3:
BAUD RATE (K)
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.596 19.231 57.471 116.279 % Error 0.00 0.02 0.02 -0.03 0.16 -0.22 0.94 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.606 19.193 57.803 114.943 % Error 0.00 0.00 0.02 0.06 -0.03 0.35 -0.22 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) 300 1200 2400 9615 19230 57142 117647 % Error -0.01 -0.04 -0.04 -0.16 -0.16 0.79 -2.12 SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2 BAUD RATE (K)
33332 8332 4165 1040 520 172 86
16665 4165 2082 520 259 86 42
8332 2082 1040 259 129 42 21
6665 1665 832 207 103 34 16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 4.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.231 58.824 111.111 % Error 0.01 0.04 0.16 0.16 0.16 2.12 -3.55 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 300 1201 2403 9615 19230 55555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 300 1201 2403 9615 19230 -- -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
3332 832 415 103 51 16 8
1665 415 207 51 25 8 --
832 207 103 25 12 -- --
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16.2.3 AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 16-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Detect must receive a byte with the value 55h (ASCII "U", which is also the LIN bus Sync character), in order to calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG begins counting up using the preselected clock source on the first rising edge of RX. After eight bits on the RX pin, or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG registers. Once the 5th edge is seen (should correspond to the Stop bit), the ABDEN bit is automatically cleared. While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes, by checking for 00h in the SPBRGH register. Refer to Table 16-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. Note 1: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature.
16.2.4
RECEIVING A SYNC (AUTO-BAUD RATE DETECT)
To receive a Sync (Auto-Baud Rate Detect): 1. Configure the EUSART for asynchronous receive. TXEN should remain clear. SPBRGH:SPBRG may be left as is. The controller should operate in either PRI_RUN or PRI_IDLE. Enable RXIF interrupts. Set RCIE, PEIE, GIE. Enable Auto-Baud Rate Detect. Set ABDEN. When the next RCIF interrupt occurs, the received baud rate has been measured. Read RCREG to clear RCIF and discard. Check SPBRGH:SPBRG for a valid value. The EUSART is ready for normal communications. Return from the interrupt. Allow the primary clock to run (PRI_RUN or PRI_IDLE). Process subsequent RCIF interrupts normally as in asynchronous reception. Remain in PRI_RUN or PRI_IDLE until communications are complete.
2. 3. 4.
5.
TABLE 16-4:
BRG16 0 0 1 1 BRGH 0 1 0 1
BRG COUNTER CLOCK RATES
BRG Counter Clock FOSC/512 FOSC/128 FOSC/128 FOSC/32
Note: During the ABD sequence, SPBRG and SPBRGH are both used as a 16-bit counter, independent of BRG16 setting.
(c) 2007 Microchip Technology Inc.
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FIGURE 16-1:
BRG Value RX pin
AUTOMATIC BAUD RATE CALCULATION
XXXXh 0000h Edge #1 Bit 1 Edge #2 Bit 3 Edge #3 Bit 5 Edge #4 Bit 7 001Ch Edge #5 Stop Bit
Start
Bit 0
Bit 2
Bit 4
Bit 6
BRG Clock Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG SPBRGH Note 1: XXXXh XXXXh 1Ch 00h Auto-Cleared
The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
16.3
EUSART Asynchronous Mode
16.3.1
The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH and BRG16 bits (TXSTA<2> and BAUDCTL<3>). Parity is not supported by the hardware, but can be implemented in software and stored as the 9th data bit. Asynchronous mode is available in all low-power modes; it is available in Sleep mode only when autowake-up on Sync Break is enabled. When in PRI_IDLE mode, no changes to the Baud Rate Generator values are required; however, other low-power mode clocks may operate at another frequency than the primary clock. Therefore, the Baud Rate Generator values may need to be adjusted. When operating in Asynchronous mode, the EUSART module consists of the following important elements: * * * * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-bit Break Character Transmit Auto-Baud Rate Detection
EUSART ASYNCHRONOUS TRANSMITTER
The EUSART transmitter block diagram is shown in Figure 16-2. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit, TXIF (PIR1<4>), is set. This interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless of the state of enable bit, TXIE, and cannot be cleared in software. Flag bit, TXIF, is not cleared immediately upon loading the Transmit Buffer register, TXREG. TXIF becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit, TRMT, is a readonly bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit, TXIF, is set when enable bit, TXEN, is set.
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To set up an Asynchronous Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. 5. 6. 7. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission).
2. 3. 4.
If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
FIGURE 16-2:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXREG Register 8 MSb (8) *** TSR Register LSb 0 Pin Buffer and Control RB1/AN5/TX/CK/INT1 pin
TXIE
Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGH SPBRG TX9 TX9D SPEN
Baud Rate Generator
FIGURE 16-3:
Write to TXREG BRG Output (Shift Clock) RB1/AN5/TX/ CK/INT1 (pin) TXIF bit (Transmit Buffer Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
bit 0
bit 1 Word 1
bit 7/8
Stop bit
1 TCY
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
(c) 2007 Microchip Technology Inc.
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FIGURE 16-4:
Write to TXREG BRG Output (Shift Clock) RB1/AN5/TX/ CK/INT1 (pin) TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) 1 TCY 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Word 1 Word 2
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Start bit
bit 0
bit 1 Word 1
bit 7/8
Stop bit
Start bit Word 2
bit 0
Note:
This timing diagram shows two consecutive transmissions.
TABLE 16-5:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCTL SPBRGH SPBRG Legend:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 6 PEIE/GIEL ADIF ADIE ADIP RX9 TX9 RCIDL Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Value on POR, BOR 0000 000x -000 -000 -000 -000 -111 -111 0000 -00x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000 Value on all other Resets 0000 000u -000 -000 -000 -000 -111 -111 0000 -00x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000
Bit 7 GIE/GIEH -- -- -- SPEN CSRC --
EUSART Transmit Register
Baud Rate Generator Register High Byte Baud Rate Generator Register Low Byte
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission.
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16.3.2 EUSART ASYNCHRONOUS RECEIVER 16.3.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT
The receiver block diagram is shown in Figure 16-5. The data is received on the RB4/AN6/RX/DT/KBI0 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. 1.
FIGURE 16-5:
EUSART RECEIVE BLOCK DIAGRAM
CREN x64 Baud Rate CLK BRG16 SPBRGH SPBRG / 64 or / 16 or /4 MSb Stop (8) 7 RSR Register *** 1 0 LSb Start OERR FERR
Baud Rate Generator
RX9 RB4/AN6/RX/DT/KBI0 Pin Buffer and Control Data Recovery RX9D RCREG Register FIFO SPEN 8 Interrupt RCIF RCIE Data Bus
(c) 2007 Microchip Technology Inc.
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To set up an Asynchronous Transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (see Section 16.2 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. 5. 6. 7. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission).
2. 3. 4.
If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
FIGURE 16-6:
RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
TABLE 16-6:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA BAUDCTL SPBRGH SPBRG Legend:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 6 PEIE/GIEL ADIF ADIE ADIP RX9 TX9 RCIDL Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF Bit 1 INT0IF TMR2IF Bit 0 RBIF TMR1IF Value on POR, BOR 0000 000x -000 -000 -000 -000 -111 -111 0000 000x 0000 0000 BRGH -- TRMT WUE TX9D ABDEN 0000 0010 -1-1 0-00 0000 0000 0000 0000 Value on all other Resets 0000 000u -000 -000 -000 -000 -111 -111 0000 000x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000
Bit 7 GIE/GIEH -- -- -- SPEN CSRC --
CCP1IE TMR2IE TMR1IE CCP1IP TMR2IP TMR1IP FERR OERR RX9D
EUSART Receive Register
Baud Rate Generator Register High Byte Baud Rate Generator Register Low Byte
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception.
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16.3.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER
During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCTL<1>). Once set, the typical receive sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.) Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 16-7) and asynchronously if the device is in Sleep mode (Figure 16-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared once a low-to-high transition is observed on the RX line, following the wakeup event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all `0's. This can be 00h (8 bytes) for standard RS-232 devices, or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient period, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART.
16.3.4.2
Special Considerations Using the WUE Bit
The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared after this when a rising edge is seen on RX/ DT. The interrupt condition is then cleared by reading the RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCIF flag is set should not be used as an indicator of the integrity of the data in RCREG. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode.
16.3.4.1
Special Considerations Using Auto-Wake-up
Since auto-wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false end-of-character
FIGURE 16-7:
OSC1
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit Set by User WUE bit RX/DT Line RCIF
Cleared by hardware
Cleared due to User Read of RCREG Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 16-8:
OSC1
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit Set by User WUE bit RX/DT Line RCIF
Enters Sleep
Cleared by hardware
Note 1 Cleared due to User Read of RCREG
Sleep Ends Note 1: 2:
If the wake-up event requires a long oscillator warm-up time, the WUE bit may be cleared while the primary clock is still starting. The EUSART remains in Idle while the WUE bit is set.
(c) 2007 Microchip Technology Inc.
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16.3.5 BREAK CHARACTER SEQUENCE
4. 5. 6. 7. The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data. Note that the value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). Note that the data value written to the TXREG for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 16-9 for the timing of the Break character sequence. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN, which will also set bit TXIF. Set the SENDB bit. Load a byte into TXREG. This triggers sending a Break signal. The Break signal is complete when TRMT is set. SENDB will also be cleared.
See Figure 16-9 for the timing of the Break signal sequence.
16.3.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (12 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 16.3.4 "Auto-Wake-up on Sync Break Character". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit before placing the EUSART in its Sleep mode.
16.3.5.1
Transmitting A Break Signal
The Enhanced USART module has the capability of sending the Break signal that is required by the LIN bus standard. The Break signal consists of a Start bit, followed by twelve `0' bits and a Stop bit. The Break signal is sent whenever the SENDB (TXSTA<3>) and TXEN (TXSTA<5>) bits are set and TXREG is loaded with data. The data written to TXREG will be ignored and all `0's will be transmitted. SENDB is automatically cleared by hardware when the Break signal has been sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. To send a Break Signal: 1. Configure the EUSART for asynchronous transmissions (steps 1-5). Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (see Section 16.2 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE.
16.3.6.1
Transmitting a Break Sync
The following sequence will send a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to set up the Break character. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG.
2. 3.
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PIC18F1220/1320
16.3.6.2
1.
Receiving a Break Sync
To receive a Break Sync: Configure the EUSART for asynchronous transmit and receive. TXEN should remain clear. SPBRGH:SPBRG may be left as is. Enable auto-wake-up. Set WUE. Enable RXIF interrupts. Set RCIE, PEIE, GIE. The controller may be placed in any power managed mode. An RCIF will be generated at the beginning of the Break signal. When the interrupt is received, read RCREG to clear RCIF and discard. Allow the controller to return to PRI_RUN mode. Wait for the RX line to go high at the end of the Break signal. Wait for any of the following: WUE to clear automatically (poll), RB4/RX to go high (poll) or for RBIF to be set (poll or interrupt). If RBIF is used, check to be sure that RB4/RX is high before continuing.
2. 3. 4. 5.
6.
Enable Auto-Baud Rate Detect. Set ABDEN. Return from the interrupt. Allow the primary clock to start and stabilize (PRI_RUN or PRI_IDLE). 9. When the next RCIF interrupt occurs, the received baud rate has been measured. Read RCREG to clear RCIF and discard. Check SPBRGH:SPBRG for a valid value. The EUSART is ready for normal communications. Return from the interrupt. Allow the primary clock to run (PRI_RUN or PRI_IDLE). 10. Process subsequent RCIF interrupts normally as in asynchronous reception. TXEN should now be set if transmissions are needed. TXIF and TXIE may be set if transmit interrupts are desired. Remain in PRI_RUN or PRI_IDLE until communications are complete. Clear TXEN and return to step 2.
7. 8.
FIGURE 16-9:
Write to TXREG BRG Output (Shift Clock) TX (pin)
SEND BREAK CHARACTER SEQUENCE
Dummy Write
Start Bit
Bit 0
Bit 1 Break
Bit 11
Stop Bit
TXIF bit
TRMT bit
SENDB
(c) 2007 Microchip Technology Inc.
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16.4 EUSART Synchronous Master Mode
Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit, TXIF (PIR1<4>), is set. The interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless of the state of enable bit, TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit, which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. To set up a Synchronous Master Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTA<4>). In addition, enable bit, SPEN (RCSTA<7>), is set in order to configure the RB1/AN5/ TX/CK/INT1 and RB4/AN6/RX/DT/KBI0 I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is selected with the SCKP bit (BAUDCTL<5>); setting SCKP sets the Idle state on CK as high, while clearing the bit sets the Idle state as low. This option is provided to support Microwire devices with this module.
16.4.1
EUSART SYNCHRONOUS MASTER TRANSMISSION
2. 3. 4. 5. 6. 7. 8.
The EUSART transmitter block diagram is shown in Figure 16-2. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available).
FIGURE 16-10:
SYNCHRONOUS TRANSMISSION
Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
RB4/AN6/RX/ DT/KBI0 pin RB1/AN5/TX/ CK/INT1 pin (SCKP = 0) RB1/AN5/TX/ CK/INT1 pin (SCKP = 1) Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit `1' Write Word 1
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 1
Word 2
Write Word 2
TXEN bit
`1'
Note:
Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
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FIGURE 16-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 2 bit 6 bit 7 RB4/AN6/RX/DT/KBI0 pin
RB1/AN5/TX/CK/INT1 pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 16-7:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCTL SPBRGH SPBRG Legend: Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Value on POR, BOR 0000 000x -000 -000 -000 -000 -111 -111 0000 -00x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000 -- Value on all other Resets 0000 000u -000 -000 -000 -000 -111 -111 0000 -00x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000
GIE/GIEH PEIE/GIEL TMR0IE -- -- -- SPEN CSRC -- ADIF ADIE ADIP RX9 TX9 RCIDL RCIF RCIE RCIP SREN TXEN
EUSART Transmit Register
Baud Rate Generator Register High Byte Baud Rate Generator Register Low Byte
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission.
(c) 2007 Microchip Technology Inc.
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16.4.2 EUSART SYNCHRONOUS MASTER RECEPTION
Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RB4/AN6/RX/DT/KBI0 pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCIE, was set. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
2.
FIGURE 16-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RB4/AN6/RX/ DT/KBI0 pin RB1/AN5/TX/ CK/INT1 pin (SCKP = 0) RB1/AN5/TX/ CK/INT1 pin (SCKP = 1) Write to bit SREN SREN bit CREN bit RCIF bit (Interrupt) Read RXREG `0'
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
`0'
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
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TABLE 16-8:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA BAUDCTL SPBRGH SPBRG Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Value on POR, BOR 0000 000x -000 -000 -000 -000 -111 -111 0000 000x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000 Value on all other Resets 0000 000u -000 -000 -000 -000 -111 -111 0000 000x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000
Bit 7
GIE/GIEH PEIE/GIEL -- -- -- SPEN CSRC -- ADIF ADIE ADIP RX9 TX9 RCIDL
EUSART Receive Register
Baud Rate Generator Register High Byte Baud Rate Generator Register Low Byte
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception.
(c) 2007 Microchip Technology Inc.
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16.5 EUSART Synchronous Slave Mode
To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the RB1/AN5/TX/CK/INT1 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode.
2. 3. 4. 5. 6. 7. 8.
16.5.1
EUSART SYNCHRONOUS SLAVE TRANSMIT
The operation of the Synchronous Master and Slave modes are identical, except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in the TXREG register. Flag bit, TXIF, will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set. If enable bit, TXIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector.
e)
TABLE 16-9:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCTL SPBRGH SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 6 PEIE/GIEL ADIF ADIE ADIP RX9 TX9 RCIDL Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Value on POR, BOR 0000 000x -000 -000 -000 -000 -111 -111 0000 000x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000 Value on all other Resets 0000 000u -000 -000 -000 -000 -111 -111 0000 000x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000
Bit 7 GIE/GIEH -- -- -- SPEN CSRC --
EUSART Transmit Register
Baud Rate Generator Register High Byte Baud Rate Generator Register Low Byte
Legend: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission.
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16.5.2 EUSART SYNCHRONOUS SLAVE RECEPTION
To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit, RCIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCIE, was set. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREG register; if the RCIE enable bit is set, the interrupt generated will wake the chip from low-power mode. If the global interrupt is enabled, the program will branch to the interrupt vector.
2. 3. 4. 5.
6.
7. 8. 9.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA BAUDCTL SPBRGH SPBRG Bit 7 GIE/GIEH -- -- -- SPEN CSRC -- Bit 6 PEIE/GIEL ADIF ADIE ADIP RX9 TX9 RCIDL Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE -- -- -- ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Value on POR, BOR 0000 000x -000 -000 -000 -000 -111 -111 0000 000x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000 Value on all other Resets 0000 000u -000 -000 -000 -000 -111 -111 0000 000x 0000 0000 0000 0010 -1-1 0-00 0000 0000 0000 0000
EUSART Receive Register
Baud Rate Generator Register High Byte Baud Rate Generator Register Low Byte
Legend: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception.
(c) 2007 Microchip Technology Inc.
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NOTES:
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17.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The module has five registers: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2)
The Analog-to-Digital (A/D) converter module has seven inputs for the PIC18F1220/1320 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time. This feature allows the user to select a new channel for conversion and to set the GO/DONE bit immediately. When the GO/DONE bit is set, the selected channel is sampled for the programmed acquisition time before a conversion is actually started. This removes the firmware overhead that may have been required to allow for an acquisition (sampling) period (see Register 17-3 and Section 17.3 "Selecting and Configuring Automatic Acquisition Time").
The ADCON0 register, shown in Register 17-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 17-2, configures the functions of the port pins. The ADCON2 register, shown in Register 17-3, configures the A/D clock source, programmed acquisition time and justification.
REGISTER 17-1:
ADCON0: A/D CONTROL REGISTER 0
R/W-0 VCFG1 bit 7 R/W-0 VCFG0 U-0 -- R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
bit 7-6
VCFG<1:0>: Voltage Reference Configuration bits
A/D VREF+ 00 01 10 11 AVDD External VREF+ AVDD External VREF+ A/D VREFAVSS AVSS External VREFExternal VREF-
bit 5 bit 4-2
Unimplemented: Read as `0' CHS2:CHS0: Analog Channel Select bits 000 = Channel 0 (AN0) 001 = Channel 1 (AN1) 010 = Channel 2 (AN2) 011 = Channel 3 (AN3) 100 = Channel 4 (AN4) 101 = Channel 5 (AN5) 110 = Channel 6 (AN6) 111 = Unimplemented(1) GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Note 1: Performing a conversion on unimplemented channels returns full-scale results. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 1
bit 0
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REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1
U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as `0' PCFG6: A/D Port Configuration bit - AN6 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' PCFG5: A/D Port Configuration bit - AN5 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' PCFG4: A/D Port Configuration bit - AN4 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' PCFG3: A/D Port Configuration bit - AN3 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' PCFG2: A/D Port Configuration bit - AN2 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' PCFG1: A/D Port Configuration bit - AN1 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' PCFG0: A/D Port Configuration bit - AN0 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified Unimplemented: Read as `0' ACQT2:ACQT0: A/D Acquisition Time Select bits 000 = 0 TAD(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD ADCS2:ADCS0: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from A/D RC oscillator)(1) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived from A/D RC oscillator)(1) Note: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. U-0 -- R/W-0 ACQT2 R/W-0 ACQT1 R/W-0 ACQT0 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 bit 0
bit 6 bit 5-3
bit 2-0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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The analog reference voltage is software selectable to either the device's positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 17-1.
FIGURE 17-1:
A/D BLOCK DIAGRAM
AVDD
CHS2:CHS0 111 110 101 100 VAIN 10-bit Converter A/D (Input Voltage) 011 010 VCFG1:VCFG0 AVDD VREFH Reference Voltage VREFL x0 x1 1x 0x AVSS 001 000
AN6(1) AN5 AN4 AN3/VREF+ AN2/VREFAN1 AN0
Note 1: I/O pins have diode protection to VDD and VSS.
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The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 17.1 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. To do an A/D Conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON2) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0 register) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. For the next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.
2.
3. 4. 5.
FIGURE 17-2:
ANALOG INPUT MODEL
VDD VT = 0.6V Rs ANx RIC 1k Sampling Switch SS RSS
VAIN
CPIN 5 pF
VT = 0.6V
ILEAKAGE 500 nA
CHOLD = 120 pF
VSS
Legend:
CPIN = input capacitance = threshold voltage VT ILEAKAGE = leakage current at the pin due to various junctions RIC = interconnect resistance SS = sampling switch CHOLD = sample/hold capacitance (from DAC) = sampling switch resistance RSS
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch (k)
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17.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 17-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. Example 17-1 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature VHOLD = = = = = 120 pF 2.5 k 1/2 LSb 5V RSS = 7 k 50C (system max.) 0V @ time = 0
17.2
A/D VREF+ and VREF- References
If external voltage references are used instead of the internal AVDD and AVSS sources, the source impedance of the VREF+ and VREF- voltage sources must be considered. During acquisition, currents supplied by these sources are insignificant. However, during conversion, the A/D module sinks and sources current through the reference sources. In order to maintain the A/D accuracy, the voltage reference source impedances should be kept low to reduce voltage changes. These voltage changes occur as reference currents flow through the reference source impedance. The maximum recommended impedance of the VREF+ and VREF- external reference voltage sources is 250.
To calculate the minimum acquisition time, Equation 17-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution.
EQUATION 17-1:
ACQUISITION TIME
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF
EQUATION 17-2:
VHOLD = or = TC
A/D MINIMUM CHARGING TIME
(VREF - (VREF/2048)) * (1 - e(-TC/CHOLD(RIC + RSS + RS))) -(CHOLD)(RIC + RSS + RS) ln(1/2048)
EXAMPLE 17-1:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ = TAMP + TC + TCOFF TAMP = 5 s TCOFF = (Temp - 25C)(0.05 s/C) (50C - 25C)(0.05 s/C) 1.25 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 s. = -(CHOLD)(RIC + RSS + RS) ln(1/2047) s TC -(120 pF) (1 k + 7 k + 2.5 k) ln(0.0004883) s 9.61 s TACQ = 5 s + 1.25 s + 9.61 s 12.86 s
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17.3 Selecting and Configuring Automatic Acquisition Time 17.4 Selecting the A/D Conversion Clock
The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT2:ACQT0 bits (ADCON2<5:3>) remain in their Reset state (`000') and is compatible with devices that do not offer programmable acquisition times. If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun.
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC oscillator
For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD (approximately 2 s, see parameter 130 for more information). Table 17-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 17-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Maximum Device Frequency PIC18F1220/1320 1.25 MHz 2.50 MHz 5.00 MHz 10.0 MHz 20.0 MHz 40.0 MHz 1.00 MHz
(1)
Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC(3) Note 1: 2: 3: 4:
ADCS2:ADCS0 000 100 001 101 010 110 x11
PIC18LF1220/1320(4) 666 kHz 1.33 MHz 2.66 MHz 5.33 MHz 10.65 MHz 21.33 MHz 1.00 MHz(2)
The RC source has a typical TAD time of 4 s. The RC source has a typical TAD time of 6 s. For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. Low-power devices only.
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17.5 Operation in Low-Power Modes 17.6 Configuring Analog Port Pins
The selection of the automatic acquisition time and the A/D conversion clock is determined, in part, by the lowpower mode clock source and frequency while in a low-power mode. If the A/D is expected to operate while the device is in a low-power mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the low-power mode clock that will be used. After the low-power mode is entered (either of the Run modes), an A/D acquisition or conversion may be started. Once an acquisition or conversion is started, the device should continue to be clocked by the same low-power mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding low-power (ANY)_IDLE mode during the conversion. If the low-power mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in the Low-Power Sleep mode requires the A/D RC clock to be selected. If bits, ACQT2:ACQT0, are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Low-Power Sleep mode. The IDLEN and SCS bits in the OSCCON register must have already been cleared prior to starting the conversion. The ADCON1, TRISA and TRISB registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the Port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits.
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17.7 A/D Conversions
Figure 17-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Low-Power Sleep mode before the conversion begins. Figure 17-4 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are set to `010' and selecting a 4 TAD acquisition time before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
FIGURE 17-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b8 b9 b3 b5 Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 17-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TACQT Cycles 1 2 3 4 1 2 b9 Automatic Acquisition Time 3 b8 4 b7
TAD Cycles 5 b6 6 b5 7 b4 8 b3 9 b2 10 b1 11 b0
Conversion Starts (Holding capacitor is disconnected)
Set GO bit (Holding capacitor continues acquiring input)
Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input.
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17.8 Use of the CCP1 Trigger
An A/D conversion can be started by the "special event trigger" of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter.
TABLE 17-2:
Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 PORTA TRISA PORTB TRISB LATB Legend: Note 1: 2: 3: Bit 7 GIE/ GIEH -- -- --
SUMMARY OF A/D REGISTERS
Bit 6 PEIE/ GIEL ADIF ADIE ADIP -- -- -- Bit 5 TMR0IE RCIF RCIE RCIP -- -- -- Bit 4 INT0IE TXIF TXIE TXIP EEIF EEIE EEIP Bit 3 RBIE -- -- -- -- -- -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP LVDIF LVDIE LVDIP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP -- -- -- Value on POR, BOR 0000 0000 -000 -000 -000 -000 -111 -111 0--0 -000--0 -001--1 -11xxxx xxxx xxxx xxxx CHS2 PCFG4 ACQT1 RA4 CHS1 PCFG3 ACQT0 RA3 CHS0 PCFG2 ADCS2 RA2 GO/DONE PCFG1 ADCS1 RA1 ADON PCFG0 ADCS0 RA0 00-0 0000 -000 0000 0-00 0000 qq0x 0000 qq-1 1111 xxxx xxxx 1111 1111 xxxx xxxx Value on all other Resets 0000 0000 -000 -000 -000 -000 -111 -111 0--0 -000--0 -001--1 -11uuuu uuuu uuuu uuuu 00-0 0000 -000 0000 0-00 0000 uu0u 0000 11-1 1111 uuuu uuuu 1111 1111 uuuu uuuu
OSCFIF OSCFIE OSCFIP
A/D Result Register High Byte A/D Result Register Low Byte VCFG1 -- ADFM RA7(3) VCFG0 PCFG6 -- RA6(2) -- PCFG5 ACQT2 RA5(1) --
TRISA7(3) TRISA6(2)
PORTA Data Direction Register
Read PORTB pins, Write LATB Latch PORTB Data Direction Register PORTB Output Data Latch
x = unknown, u = unchanged, q = depends on CONFIG1H<3:0>, - = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. RA5 port bit is available only as an input pin when the MCLRE bit in the configuration register is `0'. RA6 and TRISA6 are available only when the primary oscillator mode selection offers RA6 as a port pin; otherwise, RA6 always reads `0', TRISA6 always reads `1' and writes to both are ignored (see CONFIG1H<3:0>). RA7 and TRISA7 are available only when the internal RC oscillator is configured as the primary oscillator in CONFIG1H<3:0>; otherwise, RA7 always reads `0', TRISA7 always reads `1' and writes to both are ignored.
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18.0 LOW-VOLTAGE DETECT
In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do "housekeeping tasks", before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect module. This module is a software programmable circuitry, where a device voltage trip point can be specified. When the voltage of the device becomes lower then the specified point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. The Low-Voltage Detect circuitry is completely under software control. This allows the circuitry to be turned off by the software, which minimizes the current consumption for the device. Figure 18-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, until the device voltage is no longer in valid operating range, to shut down the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. The difference, TB - TA, is the total time for shutdown. The block diagram for the LVD module is shown in Figure 18-2 (following page). A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage crosses the set point (is lower than), the LVDIF bit is set. Each node in the resistor divider represents a "trip point" voltage. The "trip point" voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2V internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 18-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>).
FIGURE 18-1:
TYPICAL LOW-VOLTAGE DETECT APPLICATION
Voltage
VA VB Legend: VA = LVD trip point VB = Minimum valid device operating voltage
Time
TA
TB
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FIGURE 18-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM
VDD LVDIN LVD Control Register
16-to-1 MUX
LVDIF
LVDEN
Internally Generated Reference Voltage 1.2V
The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits, LVDL3:LVDL0, are set to `1111'. In this state, the comparator input is multiplexed from the external input pin,
LVDIN (Figure 18-3). This gives users flexibility, because it allows them to configure the Low-Voltage Detect interrupt to occur at any voltage in the valid operating range.
FIGURE 18-3:
LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD VDD LVD Control Register LVDIN 16-to-1 MUX LVDEN LVD
Externally Generated Trip Point
VxEN BODEN
EN BGAP
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18.1 Control Register
The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry.
REGISTER 18-1:
LVDCON REGISTER
U-0 -- bit 7 U-0 -- R-0 IRVST R/W-0 LVDEN R/W-0 LVDL3 R/W-1 LVDL2 R/W-0 LVDL1 R/W-1 LVDL0 bit 0
bit 7-6 bit 5
Unimplemented: Read as `0' IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit LVDL3:LVDL0: Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.04V-5.15V 1101 = 3.76V-4.79V 1100 = 3.58V-4.56V 1011 = 3.41V-4.34V 1010 = 3.23V-4.11V 1001 = 3.14V-4.00V 1000 = 2.96V-3.77V 0111 = 2.70V-3.43V 0110 = 2.53V-3.21V 0101 = 2.43V-3.10V 0100 = 2.25V-2.86V 0011 = 2.16V-2.75V 0010 = 1.99V-2.53V 0001 = Reserved 0000 = Reserved Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage of the device, are not tested.
bit 4
bit 3-0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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18.2 Operation
Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. The following steps are needed to set up the LVD module: 1. Write the value to the LVDL3:LVDL0 bits (LVDCON register), which selects the desired LVD trip point. Ensure that LVD interrupts are disabled (the LVDIE bit is cleared or the GIE bit is cleared). Enable the LVD module (set the LVDEN bit in the LVDCON register). Wait for the LVD module to stabilize (the IRVST bit to become set). Clear the LVD interrupt flag, which may have falsely become set, until the LVD module has stabilized (clear the LVDIF bit). Enable the LVD interrupt (set the LVDIE and the GIE bits).
2. 3. 4. 5.
6.
Figure 18-4 shows typical waveforms that the LVD module may be used to detect.
FIGURE 18-4:
CASE 1:
LOW-VOLTAGE DETECT WAVEFORMS
LVDIF may not be set. VDD VLVD LVDIF
Enable LVD Internally Generated Reference Stable TIVRST LVDIF cleared in software
CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIVRST
LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists
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18.2.1 REFERENCE VOLTAGE SET POINT
18.3
Operation During Sleep
The internal reference voltage of the LVD module may be used by other internal circuitry (the programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter 36. The low-voltage interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 18-4.
When enabled, the LVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled.
18.4
Effects of a Reset
18.2.2
CURRENT CONSUMPTION
A device Reset forces all registers to their Reset state. This forces the LVD module to be turned off.
When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter D022B.
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NOTES:
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19.0 SPECIAL FEATURES OF THE CPU
The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate configuration register bits.
PIC18F1220/1320 devices include several features intended to maximize system reliability, minimize cost through elimination of external components and offer code protection. These are: * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * ID Locations * In-Circuit Serial Programming Several oscillator options are available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. These are discussed in detail in Section 2.0 "Oscillator Configurations". A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F1220/1320 devices have a Watchdog Timer, which is either permanently enabled via the configuration bits, or software controlled (if configured as disabled).
19.1
Configuration Bits
The configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes. Programming the configuration registers is done in a manner similar to programming the Flash memory. The EECON1 register WR bit starts a self-timed write to the configuration register. In normal operation mode, a TBLWT instruction, with the TBLPTR pointing to the configuration register, sets up the address and the data for the configuration register write. Setting the WR bit starts a long write to the configuration register. The configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. For additional details on Flash programming, refer to Section 6.5 "Writing to Flash Program Memory".
TABLE 19-1:
File Name 300001h 300002h 300003h 300005h 300006h 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh 3FFFFFh Legend: Note 1:
CONFIGURATION BITS AND DEVICE IDS
Bit 7 IESO -- -- MCLRE DEBUG -- CPD -- WRTD -- -- DEV2 DEV10 Bit 6 FSCM -- -- -- -- -- CPB -- WRTB -- EBTRB DEV1 DEV9 Bit 5 -- -- -- -- -- -- -- -- WRTC -- -- DEV0 DEV8 Bit 4 -- -- -- -- -- -- -- -- -- -- REV4 DEV7 Bit 3 FOSC3 BORV1 -- -- -- -- -- -- -- -- REV3 DEV6 Bit 2 FOSC2 BORV0 -- LVP -- -- -- -- -- -- REV2 DEV5 Bit 1 FOSC1 BOR -- -- CP1 -- WRT1 -- EBTR1 -- REV1 DEV4 Bit 0 FOSC0 PWRTEN WDT -- STVR CP0 -- WRT0 -- EBTR0 -- REV0 DEV3 Default/ Unprogrammed Value 11-- 1111 ---- 1111 ---1 1111 1--- ---1--- -1-1 ---- --11 11-- ------- --11 111- ------- --11 -1-- ---xxxx xxxx(1) 0000 0111
CONFIG1H CONFIG2L CONFIG2H CONFIG3H CONFIG4L CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H DEVID2
(1)
WDTPS3 WDTPS2 WDTPS1 WDTPS0
3FFFFEh DEVID1(1)
x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as `0'. See Register 19-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
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REGISTER 19-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-1 IESO bit 7 bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled FSCM: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Unimplemented: Read as `0' FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 1001 = Internal RC oscillator, CLKO function on RA6 and port function on RA7 1000 = Internal RC oscillator, port function on RA6 and port function on RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed R/P-1 FSCM U-0 -- U-0 -- R/P-1 FOSC3 R/P-1 FOSC2 R/P-1 FOSC1 R/P-1 FOSC0 bit 0
bit 6
bit 5-4 bit 3-0
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REGISTER 19-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0 -- bit 7 bit 7-4 bit 3-2 Unimplemented: Read as `0' BORV1:BORV0: Brown-out Reset Voltage bits 11 = Reserved 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V BOR: Brown-out Reset Enable bit(1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/P-1 BORV1 R/P-1 BORV0 R/P-1 BOR R/P-1 PWRTEN bit 0
bit 1
bit 0
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REGISTER 19-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0 -- bit 7 bit 7-5 bit 4-1 Unimplemented: Read as `0' WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDT: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U-0 -- U-0 -- R/P-1 WDTPS3 R/P-1 WDTPS2 R/P-1 WDTPS1 R/P-1 WDTPS0 R/P-1 WDTEN bit 0
bit 0
U = Unimplemented bit, read as `0' u = Unchanged from programmed state
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REGISTER 19-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1 MCLRE bit 7 bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled, RA5 input pin disabled 0 = RA5 input pin enabled, MCLR disabled Unimplemented: Read as `0' Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 6-0
REGISTER 19-5:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1 DEBUG bit 7 U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 LVP U-0 -- R/P-1 STVR bit 0
bit 7
DEBUG: Background Debugger Enable bit (see note) 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug Unimplemented: Read as `0' LVP: Low-Voltage ICSP Enable bit 1 = Low-Voltage ICSP enabled 0 = Low-Voltage ICSP disabled Unimplemented: Read as `0' STVR: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed Note:
bit 6-3 bit 2
bit 1 bit 0
The Timer1 oscillator shares the T1OSI and T1OSO pins with the PGD and PGC pins used for programming and debugging. When using the Timer1 oscillator, In-Circuit Serial Programming (ICSP) may not function correctly (high voltage or low voltage), or the In-Circuit Debugger (ICD) may not communicate with the controller. As a result of using either ICSP or ICD, the Timer1 crystal may be damaged. If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead) or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation.
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PIC18F1220/1320
REGISTER 19-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
U-0 -- bit 7 bit 7-2 bit 1 Unimplemented: Read as `0' CP1: Code Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not code-protected 0 = Block 1 (001000-001FFFh) code-protected CP0: Code Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not code-protected 0 = Block 0 (00200-000FFFh) code-protected CP1: Code Protection bit (PIC18F1220) 1 = Block 1 (000800-000FFFh) not code-protected 0 = Block 1 (000800-000FFFh) code-protected CP0: Code Protection bit (PIC18F1220) 1 = Block 0 (000200-0007FFh) not code-protected 0 = Block 0 (000200-0007FFh) code-protected Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/C-1 -- R/C-1 -- R/C-1 CP1 R/C-1 CP0 bit 0
bit 0
bit 1
bit 0
REGISTER 19-7:
CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1 CPD bit 7 R/C-1 CPB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7
CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected CPB: Boot Block Code Protection bit 1 = Boot Block (000000-0001FFh) not code-protected 0 = Boot Block (000000-0001FFh) code-protected Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed
bit 6
bit 5-0
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REGISTER 19-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0 -- bit 7 bit 7-2 bit 1 Unimplemented: Read as `0' WRT1: Write Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not write-protected 0 = Block 1 (001000-001FFFh) write-protected WRT0: Write Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not write-protected 0 = Block 0 (00200-000FFFh) write-protected WRT1: Write Protection bit (PIC18F1220) 1 = Block 1 (000800-000FFFh) not write-protected 0 = Block 1 (000800-000FFFh) write-protected WRT0: Write Protection bit (PIC18F1220) 1 = Block 0 (000200-0007FFh) not write-protected 0 = Block 0 (000200-0007FFh) write-protected Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 WRT1 R/P-1 WRT0 bit 0
bit 0
bit 1
bit 0
REGISTER 19-9:
CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
R/P-1 WRTD bit 7 R/P-1 WRTB R-1 WRTC U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7
WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected WRTB: Boot Block Write Protection bit 1 = Boot Block (000000-0001FFh) not write-protected 0 = Boot Block (000000-0001FFh) write-protected WRTC: Configuration Register Write Protection bit 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected Note: This bit is read-only in normal execution mode; it can be written only in Program mode.
bit 6
bit 5
bit 4-0
Unimplemented: Read as `0' Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed
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REGISTER 19-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0 -- bit 7 bit 7-2 bit 1 Unimplemented: Read as `0' EBTR1: Table Read Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not protected from table reads executed in other blocks 0 = Block 1 (001000-001FFFh) protected from table reads executed in other blocks EBTR0: Table Read Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not protected from table reads executed in other blocks 0 = Block 0 (00200-000FFFh) protected from table reads executed in other blocks EBTR1: Table Read Protection bit (PIC18F1220) 1 = Block 1 (000800-000FFFh) not protected from table reads executed in other blocks 0 = Block 1 (000800-000FFFh) protected from table reads executed in other blocks EBTR0: Table Read Protection bit (PIC18F1220) 1 = Block 0 (000200-0007FFh) not protected from table reads executed in other blocks 0 = Block 0 (000200-0007FFh) protected from table reads executed in other blocks Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 EBTR1 R/P-1 EBTR0 bit 0
bit 0
bit 1
bit 0
REGISTER 19-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as `0' EBTRB: Boot Block Table Read Protection bit 1 = Boot Block (000000-0001FFh) not protected from table reads executed in other blocks 0 = Boot Block (000000-0001FFh) protected from table reads executed in other blocks Unimplemented: Read as `0' Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed R/P-1 EBTRB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 5-0
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REGISTER 19-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1220/1320 DEVICES
R DEV2 bit 7 bit 7-5 DEV2:DEV0: Device ID bits 111 = PIC18F1220 110 = PIC18F1320 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed R DEV1 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0
bit 4-0
REGISTER 19-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F1220/1320 DEVICES
R DEV10 bit 7 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. 0000 0111 = PIC18F1220/1320 devices Note: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified by using the entire DEV10:DEV0 bit sequence. R DEV9 R DEV8 R DEV7 R DEV6 R DEV5 R DEV4 R DEV3 bit 0
Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed
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19.2 Watchdog Timer (WDT)
For PIC18F1220/1320 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: execute a SLEEP or CLRWDT instruction, the IRCF bits (OSCCON<6:4>) are changed or a clock failure has occurred. Adjustments to the internal oscillator clock period using the OSCTUNE register also affect the period of the WDT by the same factor. For example, if the INTRC period is increased by 3%, then the WDT period is increased by 3%. Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits (OSCCON<6:4>) clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed the postscaler count will be cleared.
19.2.1
CONTROL REGISTER
Register 19-14 shows the WDTCON register. This is a readable and writable register, which contains a control bit that allows software to override the WDT enable configuration bit, only if the configuration bit has disabled the WDT.
FIGURE 19-1:
SWDTEN WDTEN INTRC Oscillator (31 kHz) CLRWDT All Device Resets WDTPS<3:0> Sleep
WDT BLOCK DIAGRAM
Enable WDT INTRC Control
WDT Counter /125 Wake-up from Sleep
Programmable Postscaler 1:1 to 1:32,768 4
Reset
WDT Reset
WDT
REGISTER 19-14: WDTCON REGISTER
U-0 -- bit 7 bit 7-1 bit 0 Unimplemented: Read as `0' SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note: Legend: R = Readable bit W = Writable bit -n = Value at POR U = Unimplemented bit, read as `0' This bit has no effect if the configuration bit, WDTEN (CONFIG2H<0>), is enabled. U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SWDTEN bit 0
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TABLE 19-2:
Name CONFIG2H RCON WDTCON Legend:
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7 -- IPEN -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 WDTPS3 RI -- Bit 3 WDTPS2 TO -- Bit 2 WDTPS2 PD -- Bit 1 WDTPS0 POR -- Bit 0 WDTEN BOR SWDTEN
Shaded cells are not used by the Watchdog Timer.
19.3
Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO bit in Configuration Register 1H (CONFIG1H<7>). Two-Speed Start-up is available only if the primary oscillator mode is LP, XT, HS or HSPLL (crystal-based modes). Other sources do not require an OST start-up delay; for these, Two-Speed Start-up is disabled. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. Because the OSCCON register is cleared on Reset events, the INTOSC (or postscaler) clock source is not initially available after a Reset event; the INTRC clock is used directly at its base frequency. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IFRC2:IFRC0, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering Sleep mode.
In all other power managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored.
19.3.1
SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed Startup, the device still obeys the normal command sequences for entering power managed modes, including serial SLEEP instructions (refer to Section 3.1.3 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS1:SCS0 bit settings and issue SLEEP commands before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. User code can also check if the primary clock source is currently providing the system clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the system clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode.
FIGURE 19-2:
INTOSC Multiplexer OSC1
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST(1) PLL Clock Output
TPLL(1) 1 2 3456 Clock Transition 7 8
CPU Clock Peripheral Clock Program Counter PC PC + 2 OSTS bit Set PC + 4 PC + 6
Wake from Interrupt Event Note
1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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19.4 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation, in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. The FSCM function is enabled by setting the Fail-Safe Clock Monitor Enable bit, FSCM (CONFIG1H<6>). When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide an instant backup clock in the event of a clock failure. Clock monitoring (shown in Figure 19-3) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral system clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the system clock source, but cleared on the rising edge of the sample clock. Since the postscaler frequency from the internal oscillator block may not be sufficiently stable, it may be desirable to select another clock configuration and enter an alternate power managed mode (see Section 19.3.1 "Special Considerations for Using Two-Speed Start-up" and Section 3.1.3 "Multiple Sleep Commands" for more details). This can be done to attempt a partial recovery, or execute a controlled shutdown. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IFRC2:IFRC0, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering Sleep mode. Adjustments to the internal oscillator block, using the OSCTUNE register, also affect the period of the FSCM by the same factor. This can usually be neglected, as the clock frequency being monitored is generally much higher than the sample clock frequency. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible.
FIGURE 19-3:
FSCM BLOCK DIAGRAM
Clock Monitor Latch (CM) (edge-triggered)
Peripheral Clock
S
Q
19.4.1
FSCM AND THE WATCHDOG TIMER
INTRC Source (32 s)
/ 64 488 Hz (2.048 ms)
C
Q
Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, Fail-Safe Clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out.
Clock Failure Detected
Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 19-4). This causes the following: * the FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>); * the system clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the Fail-Safe condition); and * the WDT is reset.
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19.4.2 EXITING FAIL-SAFE OPERATION 19.4.3
The Fail-Safe condition is terminated by either a device Reset, or by entering a power managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTOSC multiplexer provides the system clock until the primary clock source becomes ready (similar to a TwoSpeed Start-up). The clock system source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The FailSafe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its Reset state until a power managed mode is entered. Entering a power managed mode by loading the OSCCON register and executing a SLEEP instruction will clear the Fail-Safe condition. When the Fail-Safe condition is cleared, the clock monitor will resume monitoring the peripheral clock.
FSCM INTERRUPTS IN POWER MANAGED MODES
As previously mentioned, entering a power managed mode clears the Fail-Safe condition. By entering a power managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-Safe monitoring of the power managed clock source resumes in the power managed mode. If an oscillator failure occurs during power managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, the device will not exit the power managed mode on oscillator failure. Instead, the device will continue to operate as before, but clocked by the INTOSC multiplexer. While in Idle mode, subsequent interrupts will cause the CPU to begin executing instructions while being clocked by the INTOSC multiplexer. The device will not transition to a different clock source until the Fail-Safe condition is cleared.
FIGURE 19-4:
Sample Clock System Clock Output CM Output (Q)
FSCM TIMING DIAGRAM
Oscillator Failure
Failure Detected OSCFIF
CM Test Note:
CM Test
CM Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
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19.4.4 POR OR WAKE FROM SLEEP
Note: The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or Low-Power Sleep mode. When the primary system clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the system clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source The same logic that prevents false oscillator failure interrupts on POR or wake from Sleep will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged.
As noted in Section 19.3.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration and enter an alternate power managed mode while waiting for the primary system clock to become stable. When the new powered managed mode is selected, the primary clock is disabled.
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19.5 Program Verification and Code Protection
Each of the three blocks has three protection bits associated with them. They are: * Code-Protect bit (CPn) * Write-Protect bit (WRTn) * External Block Table Read bit (EBTRn) Figure 19-5 shows the program memory organization for 4 and 8-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 19-3.
The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC devices. The user program memory is divided into three blocks. One of these is a boot block of 512 bytes. The remainder of the memory is divided into two blocks on binary boundaries.
FIGURE 19-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F1220/1320
MEMORY SIZE/DEVICE Address Range 000000h 0001FFh 000200h 4 Kbytes (PIC18F1220) Boot Block 8 Kbytes (PIC18F1320) Boot Block Address Range Block Code Protection Controlled By:
Block Code Protection Controlled By: CPB, WRTB, EBTRB
000000h CPB, WRTB, EBTRB 0001FFh 000200h
CP0, WRT0, EBTR0 0007FFh 000800h CP1, WRT1, EBTR1 000FFFh 001000h
Block 0 Block 0 Block 1 000FFFh 001000h CP0, WRT0, EBTR0
Block 1
CP1, WRT1, EBTR1
(Unimplemented Memory Space)
Unimplemented Read `0's
001FFFh 002000h
Unimplemented Read `0's 1FFFFFh 1FFFFFh
(Unimplemented Memory Space)
TABLE 19-3:
300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh
SUMMARY OF CODE PROTECTION REGISTERS
Bit 7 -- CPD -- WRTD -- -- Bit 6 -- CPB -- WRTB -- EBTRB Bit 5 -- -- -- WRTC -- -- Bit 4 -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- Bit 1 CP1 -- WRT1 -- EBTR1 -- Bit 0 CP0 -- WRT0 -- EBTR0 --
File Name CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H
Legend: Shaded cells are unimplemented.
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19.5.1 PROGRAM MEMORY CODE PROTECTION
Note: The program memory may be read to, or written from, any location using the table read and table write instructions. The device ID may be read with table reads. The configuration registers may be read and written with the table read and table write instructions. In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn configuration bit is `0'. The EBTRn bits control table reads. For a block of user memory with the EBTRn bit set to `0', a table read instruction that executes from within that block is allowed to read. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading `0's. Figures 19-6 through 19-8 illustrate table write and table read protection. Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full Chip Erase or Block Erase function. The full Chip Erase and Block Erase functions can only be initiated via ICSP or an external programmer.
FIGURE 19-6:
TABLE WRITE (WRTn) DISALLOWED: PIC18F1320
Program Memory 000000h 0001FFh 000200h WRTB, EBTRB = 11 Configuration Bit Settings
Register Values
TBLPTR = 0002FFh WRT0, EBTR0 = 01 PC = 0007FEh TBLWT *
000FFFh 001000h PC = 0017FEh TBLWT * WRT1, EBTR1 = 11
001FFFh Results: All table writes disabled to Blockn whenever WRTn = 0.
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FIGURE 19-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED: PIC18F1320
Program Memory 000000h WRTB, EBTRB = 11 0001FFh 000200h TBLPTR = 0002FFh WRT0, EBTR0 = 10 Configuration Bit Settings Register Values
000FFFh 001000h
PC = 001FFEh
TBLRD * 001FFFh
WRT1, EBTR1 = 11
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of `0'.
FIGURE 19-8:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED: PIC18F1320
Program Memory 000000h WRTB, EBTRB = 11 0001FFh 000200h Configuration Bit Settings
Register Values
TBLPTR = 0002FFh PC = 0007FEh TBLRD *
WRT0, EBTR0 = 10
000FFFh 001000h
WRT1, EBTR1 = 11 001FFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR.
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19.5.2 DATA EEPROM CODE PROTECTION TABLE 19-4:
Signal PGD PGC MCLR VDD VSS PGM
ICSP/ICD CONNECTIONS
Pin Notes Shared with T1OSC - protect crystal Shared with T1OSC - protect crystal
The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM, regardless of the protection bit settings.
RB7/PGD/T1OSI/ P1D/KBI3 RB6/PGC/T1OSO/ T13CKI/P1C/KBI2 MCLR/VPP/RA5 VDD VSS RB5/PGM/KBI1
19.5.3
CONFIGURATION REGISTER PROTECTION
The configuration registers can be write-protected. The WRTC bit controls protection of the configuration registers. In normal execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer.
Optional - pull RB5 low is LVP enabled
19.8
In-Circuit Debugger
19.6
ID Locations
Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions, or during program/verify. The ID locations can be read when the device is code-protected.
When the DEBUG bit in configuration register, CONFIG4L, is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 19-5 shows which resources are required by the background debugger.
TABLE 19-5:
I/O pins: Stack:
DEBUGGER RESOURCES
RB6, RB7 2 levels 512 bytes 10 bytes
19.7
In-Circuit Serial Programming
Program Memory: Data Memory:
PIC18F1220/1320 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed (see Table 19-4). Note: The Timer1 oscillator shares the T1OSI and T1OSO pins with the PGD and PGC pins used for programming and debugging. When using the Timer1 oscillator, In-Circuit Serial Programming (ICSP) may not function correctly (high voltage or low voltage), or the In-Circuit Debugger (ICD) may not communicate with the controller. As a result of using either ICSP or ICD, the Timer1 crystal may be damaged. If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead), or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation.
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies (see the note following Section 19.7 "In-Circuit Serial Programming" for more information).
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19.9 Low-Voltage ICSP Programming
The LVP bit in configuration register, CONFIG4L, enables Low-Voltage Programming (LVP). When LVP is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP/RA5 pin, but the RB5/PGM/KBI1 pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. LVP is enabled in erased devices. While programming using LVP, VDD is applied to the MCLR/VPP/RA5 pin as in normal execution mode. To enter Programming mode, VDD is applied to the PGM pin. Note 1: High-voltage programming is always available, regardless of the state of the LVP bit or the PGM pin, by applying VIHH to the MCLR pin. 2: When Low-Voltage Programming is enabled, the RB5 pin can no longer be used as a general purpose I/O pin. 3: When LVP is enabled, externally pull the PGM pin to VSS to allow normal program execution. If Low-Voltage Programming mode will not be used, the LVP bit can be cleared and RB5/PGM/KBI1 becomes available as the digital I/O pin RB5. The LVP bit may be set or cleared only when using standard high-voltage programming (VIHH applied to the MCLR/VPP/RA5 pin). Once LVP has been disabled, only the standard highvoltage programming is available and must be used to program the device. Memory that is not code-protected can be erased, using either a Block Erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a Block Erase is required. If a Block Erase is to be performed when using Low-Voltage Programming, the device must be supplied with VDD of 4.5V to 5.5V.
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NOTES:
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20.0 INSTRUCTION SET SUMMARY
The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for three double-word instructions. These three instructions were made double-word instructions so that all the required information is available in these 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 20-1 shows the general formats that the instructions can have. All examples use the format `nnh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 20-1, lists the instructions recognized by the Microchip Assembler (MPASMTM). Section 20.2 "Instruction Set" provides a description of each instruction. The PIC18 instruction set adds many enhancements to the previous PIC instruction sets, while maintaining an easy migration from these PIC instruction sets. Most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations
The PIC18 instruction set summary in Table 20-1 lists byte-oriented, bit-oriented, literal and control operations. Table 20-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a')
The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a')
20.1
Read-Modify-Write Operations
The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--')
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified and the result is stored according to either the instruction or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a "BCF PORTB,1" instruction will read PORTB, clear bit 1 of the data, then write the result back to PORTB. The read operation would have the unintended result that any condition that sets the RBIF flag would be cleared. The R-M-W operation may also copy the level of an input pin to its corresponding output latch.
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TABLE 20-1:
Field a
OPCODE FIELD DESCRIPTIONS
Description RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7). Bank Select Register. Used to select the current RAM bank. Destination select bit d = 0: store result in WREG d = 1: store result in file register f Destination either the WREG register or the specified register file location. 8-bit register file address (0x00 to 0xFF). 12-bit register file address (0x000 to 0xFFF). This is the source address. 12-bit register file address (0x000 to 0xFFF). This is the destination address. Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). Label name. The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: No change to register (such as TBLPTR with table reads and writes) Post-Increment register (such as TBLPTR with table reads and writes) Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) The relative address (2's complement number) for relative branch instructions, or the direct address for call/branch and return instructions. Product of Multiply High Byte. Product of Multiply Low Byte. Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) Unused or unchanged. Working register (accumulator). Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 21-bit Table Pointer (points to a program memory location). 8-bit Table Latch. Top-of-Stack. Program Counter. Program Counter Low Byte. Program Counter High Byte. Program Counter High Byte Latch. Program Counter Upper Byte Latch. Global Interrupt Enable bit. Watchdog Timer. Time-out bit. Power-down bit. ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. Optional. Contents. Assigned to. Register bit field. In the set of. User defined term (font is Courier).
bbb BSR d
dest f fs fd k label mm * *+ *+* n PRODH PRODL s
u WREG x
TBLPTR TABLAT TOS PC PCL PCH PCLATH PCLATU GIE WDT TO PD C, DC, Z, OV, N [ ( <> italics ] )
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FIGURE 20-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 15 10 9 87 OPCODE d a 0 f (FILE #) Example Instruction
ADDWF MYREG, W, B
d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 12 11 1111 f (Destination FILE #) 0 f (Source FILE #) 0
MOVFF MYREG1, MYREG2
f = 12-bit file register address Bit-oriented file register operations 15 12 11 98 7 f (FILE #) 0
OPCODE b (BIT #) a
BSF MYREG, bit, B
b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 OPCODE k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 12 11 n<19:8> (literal) 87 n<7:0> (literal) 0 0 8 7 k (literal) 0
MOVLW 0x7F
GOTO Label
n = 20-bit immediate value 15 OPCODE 15 12 11 n<19:8> (literal) S = Fast bit 15 OPCODE 15 OPCODE 11 10 n<10:0> (literal) 87 n<7:0> (literal) 0 0 87 S n<7:0> (literal) 0 0
CALL MYFUNC
BRA MYFUNC
BC MYFUNC
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TABLE 20-1:
Mnemonic, Operands
PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1
None None C, DC, Z, OV, N 1, 2 C, Z, N Z, N 1, 2 C, Z, N Z, N None C, DC, Z, OV, N 1, 2
f, d, a SUBWF SUBWFB f, d, a SWAPF TSTFSZ XORWF BCF BSF BTFSC BTFSS BTG f, d, a f, a f, d, a f, b, a f, b, a f, b, a f, b, a f, d, a
0101 11da 0101 10da
ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N 1, 2 ffff None ffff None ffff Z, N ffff ffff ffff ffff ffff None None None None None 4 1, 2
1 0011 10da 1 (2 or 3) 0110 011a 1 0001 10da 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba
BIT-ORIENTED FILE REGISTER OPERATIONS 1, 2 1, 2 3, 4 3, 4 1, 2
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
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TABLE 20-1:
Mnemonic, Operands CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable Return with literal in WREG Return from Subroutine Go into Standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None TO, PD C None
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
CLRWDT -- DAW -- GOTO n NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP -- -- -- -- n s k s --
0000 1100 0000 0000 0000 0000
None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD
4
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
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TABLE 20-1:
Mnemonic, Operands LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* k k k f, k k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1000 1001 1010 1011 1100 1101 1110 1111 C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N None None None None None None None None
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
DATA MEMORY PROGRAM MEMORY OPERATIONS Table read 2 Table read with post-increment Table read with post-decrement Table read with pre-increment Table write 2 (5) Table write with post-increment Table write with post-decrement Table write with pre-increment
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
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20.2
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Set
ADD literal to W [ label ] ADDLW 0 k 255 (W) + k W N, OV, C, DC, Z
0000 1111 kkkk kkkk
ADDWF k Syntax: Operands:
ADD W to f [ label ] ADDWF 0 f 255 d [0,1] a [0,1] (W) + (f) dest N, OV, C, DC, Z
0010 01da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
The contents of W are added to the 8-bit literal `k' and the result is placed in W. 1 1 Q2
Read literal `k' ADDLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x15
Q4
Write to W
Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR is used. 1 1 Q2
Read register `f' ADDWF
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
W W = =
Before Instruction
0x10 0x25
Q3
Process Data REG, W
Q4
Write to destination
After Instruction Example:
W REG W REG = = = =
Before Instruction
0x17 0xC2 0xD9 0xC2
After Instruction
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ADDWFC Syntax: Operands: ADD W and Carry bit to f [ label ] ADDWFC 0 f 255 d [0,1] a [0,1] (W) + (f) + (C) dest N, OV, C, DC, Z
0010 00da ffff ffff
ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. k W N, Z
0000 1011 kkkk kkkk
f [,d [,a]]
k
Operation: Status Affected: Encoding: Description:
Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden. 1 1
The contents of W are AND'ed with the 8-bit literal `k'. The result is placed in W. 1 1 Q2
Read literal `k' ANDLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x5F
Q4
Write to W
Words: Cycles: Q Cycle Activity: Q1
Decode
Example: Q2
Read register `f' ADDWFC 1 0x02 0x4D 0 0x02 0x50
Q3
Process Data REG, W
Q4
Write to destination
Before Instruction
W W = = 0xA3 0x03
After Instruction
Example:
Carry bit = REG = W =
Before Instruction
After Instruction
Carry bit = REG = W =
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ANDWF Syntax: Operands: AND W with f [ label ] ANDWF 0 f 255 d [0,1] a [0,1] (W) .AND. (f) dest N, Z
0001 01da ffff ffff
BC f [,d [,a]] Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Carry [ label ] BC n -128 n 127 if Carry bit is `1' (PC) + 2 + 2n PC None
1110 0010 nnnn nnnn
Operation: Status Affected: Encoding: Description:
The contents of W are AND'ed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden (default). 1 1 Q2
Read register `f' ANDWF
If the Carry bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: Q1
Decode
Words: Cycles: Q3
Process Data REG, W
Q4
Write to destination
Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Example:
W REG W REG = = = =
Before Instruction
0x17 0xC2 0x02 0xC2
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BC JUMP
Q4
No operation
After Instruction
Example:
PC
Before Instruction
address (HERE) 1; address (JUMP) 0; address (HERE + 2)
After Instruction
If Carry PC If Carry PC
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BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 255 0b7 a [0,1] 0 f None
1001 bbba ffff ffff
BN f,b[,a] Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Negative [ label ] BN n -128 n 127 if Negative bit is `1' (PC) + 2 + 2n PC None
1110 0110 nnnn nnnn
Operation: Status Affected: Encoding: Description:
Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' BCF = =
Words: Cycles: Q Cycle Activity: Q1
Decode
If the Negative bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q3
Process Data FLAG_REG, 7 0xC7 0x47 No operation
Q4
Write register `f'
Q Cycle Activity: If Jump: Q1
Decode
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Example:
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BN Jump
Q4
No operation
Example:
PC
Before Instruction
address (HERE) 1; address (Jump) 0; address (HERE + 2)
After Instruction
If Negative PC If Negative PC
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BNC Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Carry [ label ] BNC -128 n 127 if Carry bit is `0' (PC) + 2 + 2n PC None
1110 0011 nnnn nnnn
BNN Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Negative [ label ] BNN -128 n 127 if Negative bit is `0' (PC) + 2 + 2n PC None
1110 0111 nnnn nnnn
n
n
If the Carry bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
If the Negative bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BNC Jump
Q4
No operation
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BNN Jump
Q4
No operation
Example:
PC
Example:
PC
Before Instruction
address (HERE) 0; address (Jump) 1; address (HERE + 2)
Before Instruction
address (HERE) 0; address (Jump) 1; address (HERE + 2)
After Instruction
If Carry PC If Carry PC
After Instruction
If Negative PC If Negative PC
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BNOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Overflow [ label ] BNOV -128 n 127 if Overflow bit is `0' (PC) + 2 + 2n PC None
1110 0101 nnnn nnnn
BNZ Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Zero [ label ] BNZ -128 n 127 if Zero bit is `0' (PC) + 2 + 2n PC None
1110 0001 nnnn nnnn
n
n
If the Overflow bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
If the Zero bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BNOV Jump address (HERE)
Q4
No operation
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BNZ Jump
Q4
No operation
Example:
PC
Example:
PC
Before Instruction After Instruction
If Overflow PC If Overflow PC 0; address (Jump) 1; address (HERE + 2)
Before Instruction
address (HERE) 0; address (Jump) 1; address (HERE + 2)
After Instruction
If Zero PC If Zero PC
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BRA Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] BRA n -1024 n 1023 (PC) + 2 + 2n PC None
1101 0nnn nnnn nnnn
BSF Syntax: Operands:
Bit Set f [ label ] BSF 0 f 255 0b7 a [0,1] 1 f None
1000 bbba ffff ffff
f,b[,a]
Operation: Status Affected: Encoding: Description:
Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2 Q2
Read literal `n' No operation
Words: Cycles: Q Cycle Activity: Q1
Decode No operation
Bit `b' in register `f' is set. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. 1 1 Q2
Read register `f' BSF = =
Words: Cycles: Q3
Process Data No operation
Q4
Write to PC No operation
Q Cycle Activity: Q1
Decode
Q3
Process Data FLAG_REG, 7 0x0A 0x8A
Q4
Write register `f'
Example: Example:
PC HERE = = BRA Jump
Before Instruction
FLAG_REG
Before Instruction
address (HERE) address (Jump)
After Instruction
FLAG_REG
After Instruction
PC
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BTFSC Syntax: Operands: Bit Test File, Skip if Clear [ label ] BTFSC f,b[,a] 0 f 255 0b7 a [0,1] skip if (f) = 0 None
1011 bbba ffff ffff
BTFSS Syntax: Operands:
Bit Test File, Skip if Set [ label ] BTFSS f,b[,a] 0 f 255 0b<7 a [0,1] skip if (f) = 1 None
1010 bbba ffff ffff
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3
Process Data
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
Q Cycle Activity: Q1
Decode
Q2
Read register `f'
Q4
No operation
If skip: Q1
No operation
If skip: Q2
No operation
Q3
No operation
Q4
No operation
Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE FALSE TRUE = = = = = No operation No operation BTFSC : :
Q4
No operation No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE FALSE TRUE = = = = = No operation No operation BTFSS : :
Q4
No operation No operation
Example:
FLAG, 1
Example:
FLAG, 1
Before Instruction
PC address (HERE) 0; address (TRUE) 1; address (FALSE)
Before Instruction
PC address (HERE) 0; address (FALSE) 1; address (TRUE)
After Instruction
If FLAG<1> PC If FLAG<1> PC
After Instruction
If FLAG<1> PC If FLAG<1> PC
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BTG Syntax: Operands: Bit Toggle f [ label ] BTG f,b[,a] 0 f 255 0b<7 a [0,1] (f) f None
0111 bbba ffff ffff
BOV Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Overflow [ label ] BOV -128 n 127 if Overflow bit is `1' (PC) + 2 + 2n PC None
1110 0100 nnnn nnnn
n
Operation: Status Affected: Encoding: Description:
Bit `b' in data memory location `f' is inverted. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' BTG = =
Words: Cycles: Q Cycle Activity: Q1
Decode
If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q3
Process Data PORTB, 4 No operation
Q4
Write register `f'
Q Cycle Activity: If Jump: Q1
Decode
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Example:
PORTB PORTB
Before Instruction:
0111 0101 [0x75] 0110 0101 [0x65]
After Instruction:
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BOV JUMP
Q4
No operation
Example:
PC
Before Instruction
address (HERE) 1; address (JUMP) 0; address (HERE + 2)
After Instruction
If Overflow PC If Overflow PC
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BZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Zero [ label ] BZ n -128 n 127 if Zero bit is `1' (PC) + 2 + 2n PC None
1110 0000 nnnn nnnn
CALL Syntax: Operands: Operation:
Subroutine Call [ label ] CALL k [,s] 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (Status) STATUSS, (BSR) BSRS None
1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8
If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, Status and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2 Q2
Read literal `k'<7:0>, No operation HERE = = = = = =
If No Jump: Q1
Decode
Words: Q2
Read literal `n' HERE = = = = =
Q3
Process Data BZ Jump
Q4
No operation
Cycles: Q Cycle Activity: Q1
Decode
Q3
Push PC to stack No operation CALL
Q4
Read literal `k'<19:8>, Write to PC No operation
Example:
PC
Before Instruction
address (HERE) 1; address (Jump) 0; address (HERE + 2)
After Instruction
If Zero PC If Zero PC
No operation
Example:
PC PC TOS WS BSRS STATUSS
THERE, FAST
Before Instruction
address (HERE) address (THERE) address (HERE + 4) W BSR Status
After Instruction
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CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Clear f [ label ] CLRF 0 f 255 a [0,1] 000h f 1Z Z
0110 101a ffff ffff
CLRWDT f [,a] Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD
0000 0000 0000 0100
Status Affected: Encoding: Description:
Clears the contents of the specified register. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' CLRF = = 0x5A 0x00
CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. 1 1 Q2
No operation CLRWDT = = = = = ? 0x00 0 1 1
Words: Cycles: Q Cycle Activity: Q1
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
Q3
Process Data FLAG_REG
Q4
Write register `f'
Decode
Example: Example: Before Instruction
FLAG_REG
Before Instruction
WDT Counter
After Instruction
WDT Counter WDT Postscaler TO PD
After Instruction
FLAG_REG
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COMF Syntax: Operands: Complement f [ label ] COMF 0 f 255 d [0,1] a [0,1] (f) dest N, Z
0001 11da ffff ffff
CPFSEQ f [,d [,a]] Syntax: Operands: Operation:
Compare f with W, skip if f = W [ label ] CPFSEQ 0 f 255 a [0,1] (f) - (W), skip if (f) = (W) (unsigned comparison) None
0110 001a ffff ffff
f [,a]
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' COMF = = = 0x13 0x13 0xEC
Words: Cycles: Q Cycle Activity: Q1
Decode
Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
Q3
Process Data REG, W
Q4
Write to destination
Words: Cycles:
Example:
REG REG W
Before Instruction After Instruction
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NEQUAL EQUAL = = = = = = No operation No operation CPFSEQ REG : : HERE ? ? W; Address (EQUAL) W; Address (NEQUAL)
Q4
No operation No operation
Example:
Before Instruction
PC Address W REG
After Instruction
If REG PC If REG PC
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CPFSGT Syntax: Operands: Operation: Compare f with W, skip if f > W [ label ] CPFSGT 0 f 255 a [0,1] (f) - (W), skip if (f) > (W) (unsigned comparison) None
0110 010a ffff ffff
CPFSLT Syntax: Operands: Operation:
Compare f with W, skip if f < W [ label ] CPFSLT 0 f 255 a [0,1] (f) - (W), skip if (f) < (W) (unsigned comparison) None
0110 000a ffff ffff
f [,a]
f [,a]
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NLESS LESS = = < = = No operation No operation CPFSLT REG : : Address (HERE) ? W; Address (LESS) W; Address (NLESS)
Q4
No operation No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NGREATER GREATER = = > = = No operation No operation CPFSGT REG : :
Q4
No operation No operation
Example:
Example:
Before Instruction
PC W
Before Instruction
PC W Address (HERE) ? W; Address (GREATER) W; Address (NGREATER)
After Instruction
If REG PC If REG PC
After Instruction
If REG PC If REG PC
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DAW Syntax: Operands: Operation: Decimal Adjust W Register [ label ] DAW None If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; If [W<7:4> > 9] or [C = 1] then (W<7:4>) + 6 W<7:4>; else (W<7:4>) W<7:4>; Status Affected: Encoding: Description: C, DC
0000 0000 0000 0111
DECF Syntax: Operands:
Decrement f [ label ] DECF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - 1 dest C, DC, N, OV, Z
0000 01da ffff ffff
Operation: Status Affected: Encoding: Description:
DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. The Carry bit may be set by DAW regardless of its setting prior to the DAW instruction. 1 1
Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' DECF = = = = 0x01 0 0x00 1
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data CNT
Q4
Write to destination
Words: Cycles: Q Cycle Activity: Q1
Decode
Example: Q2
Read register W DAW = = = = = = 0xA5 0 0 0x05 1 0
Q3
Process Data
Q4
Write W
Before Instruction
CNT Z CNT Z
Example 1:
W C DC W C DC
After Instruction
Before Instruction
After Instruction
Example 2: Before Instruction
W C DC W C DC = = = = = = 0xCE 0 0 0x34 1 0
After Instruction
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DECFSZ Syntax: Operands: Decrement f, skip if 0 [ label ] DECFSZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None
0010 11da ffff ffff
DCFSNZ Syntax: Operands:
Decrement f, skip if not 0 [ label ] DCFSNZ 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result 0 None
0100 11da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a twocycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
If skip: Q1
No operation
If skip: Q2
No operation
Q3
No operation
Q4
No operation
Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE CONTINUE No operation No operation DECFSZ GOTO
Q4
No operation No operation CNT LOOP
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE ZERO NZERO = = = = = No operation No operation DCFSNZ TEMP : : ?
Q4
No operation No operation
Example:
Example:
Before Instruction
PC CNT If CNT PC If CNT PC = = = = = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2)
Before Instruction
TEMP
After Instruction
After Instruction
TEMP If TEMP PC If TEMP PC TEMP - 1, 0; Address (ZERO) 0; Address (NZERO)
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GOTO Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Unconditional Branch [ label ] GOTO k 0 k 1048575 k PC<20:1> None
1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8
INCF Syntax: Operands:
Increment f [ label ] INCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest C, DC, N, OV, Z
0010 10da ffff ffff
Operation: Status Affected: Encoding: Description:
GOTO allows an unconditional branch anywhere within the entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. 2 2
Words: Cycles: Q Cycle Activity: Q1
Decode
The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' INCF = = = = = = = = 0xFF 0 ? ? 0x00 1 1 1
Words: Q2
Read literal `k'<7:0>, No operation GOTO THERE Address (THERE)
Q3
No operation No operation
Q4
Read literal `k'<19:8>, Write to PC No operation
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data CNT
Q4
Write to destination
No operation
Example:
PC =
Example:
CNT Z C DC CNT Z C DC
After Instruction
Before Instruction
After Instruction
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INCFSZ Syntax: Operands: Increment f, skip if 0 [ label ] INCFSZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None
0011 11da ffff ffff
INFSNZ Syntax: Operands:
Increment f, skip if not 0 [ label ] INFSNZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None
0100 10da ffff ffff
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
If skip: Q1
No operation
If skip: Q2
No operation
Q3
No operation
Q4
No operation
Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NZERO ZERO = = = = = No operation No operation INCFSZ : : CNT
Q4
No operation No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE ZERO NZERO = = No operation No operation INFSNZ REG
Q4
No operation No operation
Example:
Example:
Before Instruction
PC CNT If CNT PC If CNT PC Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO)
Before Instruction
PC REG If REG PC If REG PC Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO)
After Instruction
After Instruction
= = =
(c) 2007 Microchip Technology Inc.
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IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k W N, Z
0000 1001 kkkk kkkk
IORWF Syntax: Operands:
Inclusive OR W with f [ label ] IORWF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (W) .OR. (f) dest N, Z
0001 00da ffff ffff
Operation: Status Affected: Encoding: Description:
The contents of W are OR'ed with the eight-bit literal `k'. The result is placed in W. 1 1 Q2
Read literal `k' IORLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x35
Q4
Write to W
Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f'
Words: Example:
W W = =
Cycles: Q Cycle Activity: Q1
Decode
Before Instruction
0x9A 0xBF
Q3
Process Data
Q4
Write to destination
After Instruction
Example:
RESULT = W =
IORWF RESULT, W 0x13 0x91 0x13 0x93
Before Instruction
After Instruction
RESULT = W =
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(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
LFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Load FSR [ label ] LFSR f,k 0f2 0 k 4095 k FSRf None
1110 1111 1110 0000 00ff k7kkk k11kkk kkkk
MOVF Syntax: Operands:
Move f [ label ] MOVF f [,d [,a]] 0 f 255 d [0,1] a [0,1] f dest N, Z
0101 00da ffff ffff
Operation: Status Affected: Encoding: Description:
The 12-bit literal `k' is loaded into the file select register pointed to by `f'. 2 2 Q2
Read literal `k' MSB Read literal `k' LSB
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data Process Data
Q4
Write literal `k' MSB to FSRfH Write literal `k' to FSRfL
Decode
The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `f', the result is placed in W. If `d' is `f', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' MOVF = = = =
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
FSR2H FSR2L
LFSR 2, 0x3AB = = 0x03 0xAB
After Instruction
Q3
Process Data REG, W 0x22 0xFF 0x22 0x22
Q4
Write W
Example:
REG W
Before Instruction
After Instruction
REG W
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MOVFF Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: Move f to f [ label ] MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None
1100 1111 ffff ffff ffff ffff ffffs ffffd
MOVLB Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
Move literal to low nibble in BSR [ label ] k BSR None
0000 0001 kkkk kkkk
MOVLB k
0 k 255
The 8-bit literal `k' is loaded into the Bank Select Register (BSR). 1 1 Q2
Read literal `k'
The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. The MOVFF instruction should not be used to modify interrupt settings while any interrupt is enabled (see page 73).
Q3
Process Data
Q4
Write literal `k' to BSR
Example:
MOVLB = =
5 0x02 0x05
Before Instruction
BSR register
After Instruction
BSR register
Words: Cycles: Q Cycle Activity: Q1
Decode
2 2 (3) Q2
Read register `f' (src) No operation No dummy read
Q3
Process Data No operation
Q4
No operation Write register `f' (dest)
Decode
Example:
REG1 REG2
MOVFF = = = =
REG1, REG2 0x33 0x11 0x33, 0x33
Before Instruction
After Instruction
REG1 REG2
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MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
Move literal to W [ label ] kW None
0000 1110 kkkk kkkk
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move W to f [ label ] MOVWF f [,a] 0 f 255 a [0,1] (W) f None
0110 111a ffff ffff
MOVLW k
0 k 255
The eight-bit literal `k' is loaded into W. 1 1 Q2
Read literal `k' MOVLW
Q3
Process Data 0x5A
Q4
Write to W
Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' MOVWF
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
W =
After Instruction
0x5A
Q3
Process Data REG
Q4
Write register `f'
Example:
W REG W REG = = = =
Before Instruction
0x4F 0xFF 0x4F 0x4F
After Instruction
(c) 2007 Microchip Technology Inc.
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MULLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply Literal with W [ label ] MULLW k 0 k 255 (W) x k PRODH:PRODL None
0000 1101 kkkk kkkk
MULWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Multiply W with f [ label ] MULWF f [,a] 0 f 255 a [0,1] (W) x (f) PRODH:PRODL None
0000 001a ffff ffff
An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. 1 1 Q2
Read literal `k'
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write registers PRODH: PRODL
An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible, but not detected. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f'
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
W PRODH PRODL
MULLW = = = = = =
0xC4 0xE2 ? ? 0xE2 0xAD 0x08
Before Instruction
Q3
Process Data
Q4
Write registers PRODH: PRODL
After Instruction
W PRODH PRODL
Example:
W REG PRODH PRODL
MULWF = = = = = = = =
REG 0xC4 0xB5 ? ? 0xC4 0xB5 0x8A 0x94
Before Instruction
After Instruction
W REG PRODH PRODL
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NEGF Syntax: Operands: Operation: Status Affected: Encoding: Description: Negate f [ label ] NEGF f [,a] 0 f 255 a [0,1] (f) + 1 f N, OV, C, DC, Z
0110 110a ffff ffff
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
No Operation [ label ] None No operation None
0000 1111 0000 xxxx 0000 xxxx 0000 xxxx
NOP
Location `f' is negated using two's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. 1 1 Q2
Read register `f' NEGF = =
No operation. 1 1 Q2
No operation
Q3
No operation
Q4
No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Example: Q3
Process Data REG, 1
Q4
Write register `f'
None.
Example:
REG REG
Before Instruction
0011 1010 [0x3A] 1100 0110 [0xC6]
After Instruction
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POP Syntax: Operands: Operation: Status Affected: Encoding: Description: Pop Top of Return Stack [ label ] None (TOS) bit bucket None
0000 0000 0000 0110
PUSH Syntax: Operands: Operation: Status Affected: Encoding: Description:
Push Top of Return Stack [ label ] None (PC + 2) TOS None
0000 0000 0000 0101
POP
PUSH
The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1 Q2
No operation POP GOTO
The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. 1 1 Q2
Push PC + 2 onto return stack PUSH = = 0x00345A 0x000124
Words: Cycles: Q Cycle Activity: Q1
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
No operation
Q4
No operation
Q3
Pop TOS value
Q4
No operation
Decode
Example:
Example:
NEW = = 0x0031A2 0x014332 TOS PC
Before Instruction
Before Instruction
TOS Stack (1 level down)
After Instruction After Instruction
TOS PC = = 0x014332 NEW PC TOS Stack (1 level down) = = = 0x000126 0x000126 0x00345A
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RCALL Syntax: Operands: Operation: Status Affected: Encoding: Description: Relative Call [ label ] RCALL -1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None
1101 1nnn nnnn nnnn
RESET n Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
Reset [ label ] None Reset all registers and flags that are affected by a MCLR Reset. All
0000 0000 1111 1111
RESET
Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2 Q2
Read literal `n' Push PC to stack
This instruction provides a way to execute a MCLR Reset in software. 1 1 Q2
Start Reset RESET Reset Value Reset Value
Q3
No operation
Q4
No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Example: Q3
Process Data
After Instruction Q4
Write to PC Registers = Flags* =
No operation
No operation HERE
No operation RCALL Jump
No operation
Example:
PC = PC = TOS =
Before Instruction
Address (HERE) Address (Jump) Address (HERE + 2)
After Instruction
(c) 2007 Microchip Technology Inc.
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RETFIE Syntax: Operands: Operation: Return from Interrupt [ label ] s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged. GIE/GIEH, PEIE/GIEL.
0000 0000 0001 000s
RETLW Syntax: Operands: Operation:
Return Literal to W [ label ] RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None
0000 1100 kkkk kkkk
RETFIE [s]
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q2
No operation
W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2 Q2
Read literal `k' No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data No operation
Q4
Pop PC from stack, Write to W No operation
No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; W contains table offset value W now has table value
Q3
No operation
Q4
Pop PC from stack Set GIEH or GIEL
No operation
No operation RETFIE 1
No operation
No operation
W = offset Begin table
Example: After Interrupt
End of table
PC W BSR Status GIE/GIEH, PEIE/GIEL
= = = = =
TOS WS BSRS STATUSS 1
Before Instruction
W W = = 0x07 value of kn
After Instruction
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RETURN Syntax: Operands: Operation: Return from Subroutine [ label ] s [0,1] (TOS) PC, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged None
0000 0000 0001 001s
RLCF Syntax: Operands:
Rotate Left f through Carry [ label ] RLCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) C, (C) dest<0> C, N, Z
0011 01da ffff ffff
RETURN [s]
Operation:
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Return from subroutine. The stack is popped and the top of the stack is loaded into the program counter. If `s'= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q2
No operation No operation
The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). C
register f
Words: Cycles: Q Cycle Activity: Q1
Decode No operation
Words: Q3
Process Data No operation
1 1 Q2
Read register `f' RLCF = = = = =
Q4
Pop PC from stack No operation
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG, W
Q4
Write to destination
Example: Example: After Interrupt
PC = TOS RETURN REG C REG W C
Before Instruction
1110 0110 0 1110 0110 1100 1100 1
After Instruction
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RLNCF Syntax: Operands: Rotate Left f (no carry) [ label ] RLNCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) dest<0> N, Z
0100 01da ffff ffff
RRCF Syntax: Operands:
Rotate Right f through Carry [ label ] RRCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) C, (C) dest<7> C, N, Z
0011 00da ffff ffff
Operation: Status Affected: Encoding: Description:
Operation:
Status Affected: Encoding: Description:
The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default).
register f
The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). C
register f
Words: Cycles: Q Cycle Activity: Q1
Decode
1 1 Words: Q2
Read register `f' RLNCF = =
1 1 Q2
Read register `f' RRCF = = = = =
Q3
Process Data REG
Q4
Write to destination
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG, W
Q4
Write to destination
Example:
REG REG
Before Instruction
1010 1011 0101 0111
Example:
REG C REG W C
After Instruction
Before Instruction
1110 0110 0 1110 0110 0111 0011 0
After Instruction
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RRNCF Syntax: Operands: Rotate Right f (no carry) [ label ] RRNCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) dest<7> N, Z
0100 00da ffff ffff
SETF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Set f [ label ] SETF 0 f 255 a [0,1] FFh f None
0110 100a ffff ffff
f [,a]
Operation: Status Affected: Encoding: Description:
The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default).
register f
The contents of the specified register are set to FFh. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' SETF = = REG 0x5A 0xFF
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write register `f'
Words: Cycles: Q Cycle Activity: Q1
Decode
1 1 Q2
Read register `f' RRNCF = =
Example: Q3
Process Data REG, 1, 0
Before Instruction Q4
Write to destination REG
After Instruction
REG
Example 1:
REG REG
Before Instruction
1101 0111 1110 1011 RRNCF = = = = REG, W
After Instruction Example 2:
W REG W REG
Before Instruction
? 1101 0111 1110 1011 1101 0111
After Instruction
(c) 2007 Microchip Technology Inc.
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SLEEP Syntax: Operands: Operation: Enter Sleep mode [ label ] SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD
0000 0000 0000 0011
SUBFWB Syntax: Operands:
Subtract f from W with borrow [ label ] SUBFWB 0 f 255 d [0,1] a [0,1] (W) - (f) - (C) dest N, OV, C, DC, Z
0101 01da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
The Power-down status bit (PD) is cleared. The Time-out status bit (TO) is set. The Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. 1 1 Words: Q2
No operation SLEEP ? ?
Words: Cycles: Q Cycle Activity: Q1
Decode
Subtract register `f' and Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f'
Q3
Process Data
Q4
Go to Sleep
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
Example:
TO = PD =
Before Instruction Example 1:
REG W C REG W C Z N
SUBFWB REG = = = = = = = = 0x03 0x02 0x01 0xFF 0x02 0x00 0x00 0x01 SUBFWB = = = = = = = = 2 5 1 2 3 1 0 0 SUBFWB = = = = = = = = 1 2 0 0 2 1 1 0
After Instruction TO = 1 0 PD = If WDT causes wake-up, this bit is cleared.
Before Instruction
After Instruction
; result is negative REG, 0, 0
Example 2:
REG W C REG W C Z N
Before Instruction
After Instruction
; result is positive REG, 1, 0
Example 3:
REG W C REG W C Z N
Before Instruction
After Instruction
; result is zero
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SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) W N, OV, C, DC, Z
0000 1000 kkkk kkkk
SUBWF Syntax: Operands:
Subtract W from f [ label ] SUBWF 0 f 255 d [0,1] a [0,1] (f) - (W) dest N, OV, C, DC, Z
0101 11da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
W is subtracted from the eight-bit literal `k'. The result is placed in W. 1 1 Q2
Read literal `k' SUBLW = = = = = = 1 ? 1 1 0 0 SUBLW = = = = = = 2 ? 0 1 1 0 SUBLW = = = = = = 3 ? FF 0 0 1 ; (2's complement) ; result is negative
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x02
Q4
Write to W
Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' SUBWF REG = = = = = = = = 3 2 ? 1 2 1 0 0
Example 1:
W C W C Z N
Words: Cycles: Q Cycle Activity: Q1
Before Instruction
After Instruction
; result is positive
Q3
Process Data
Q4
Write to destination
Decode
Example 1:
0x02 REG W C REG W C Z N
Example 2:
W C W C Z N
Before Instruction
Before Instruction
After Instruction
; result is zero
After Instruction
; result is positive
Example 3:
W C W C Z N
0x02
Example 2:
REG W C REG W C Z N = = = = = = = =
SUBWF REG, W 2 2 ? 2 0 1 1 0
Before Instruction
Before Instruction
After Instruction
After Instruction
; result is zero
Example 3:
REG W C REG W C Z N = = = = = = = =
SUBWF REG 0x01 0x02 ? 0xFFh ;(2's complement) 0x02 0x00 ;result is negative 0x00 0x01
Before Instruction
After Instruction
(c) 2007 Microchip Technology Inc.
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SUBWFB Syntax: Operands: Subtract W from f with Borrow [ label ] SUBWFB 0 f 255 d [0,1] a [0,1] (f) - (W) - (C) dest N, OV, C, DC, Z
0101 10da ffff ffff
SWAPF Syntax: Operands:
Swap f [ label ] SWAPF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None
0011 10da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
Subtract W and the Carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' SUBWFB = = = = = = = = 0x19 0x0D 0x01 0x0C 0x0D 0x01 0x00 0x00
The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' SWAPF = = 0x53 0x35
Words: Cycles: Q Cycle Activity: Q1
Decode
Words: Cycles: Q3
Process Data REG, 1, 0 (0001 1001) (0000 1101)
Q4
Write to destination
Q Cycle Activity: Q1
Decode
Q3
Process Data REG
Q4
Write to destination
Example 1:
REG W C REG W C Z N
Example:
REG REG
Before Instruction
Before Instruction After Instruction
After Instruction
(0000 1011) (0000 1101) ; result is positive
Example 2:
REG W C REG W C Z N = = = = = = = =
SUBWFB REG, 0, 0 0x1B 0x1A 0x00 0x1B 0x00 0x01 0x01 0x00 SUBWFB = = = = = = = = 0x03 0x0E 0x01 0xF5 0x0E 0x00 0x00 0x01 (0001 1011) (0001 1010)
Before Instruction
After Instruction
(0001 1011) ; result is zero REG, 1, 0 (0000 0011) (0000 1101)
Example 3:
REG W C REG W C Z N
Before Instruction
After Instruction
(1111 0100) ; [2's comp] (0000 1101) ; result is negative
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TBLRD Syntax: Operands: Operation: Table Read [ label ] TBLRD ( *; *+; *-; +*) None if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) - 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT;
0000 0000 0000 10nn nn = 0* = 1*+ = 2*= 3+*
TBLRD Example 1:
Table Read (Continued)
TBLRD *+ ; = = = = = TBLRD +* ; = = = = = = 0xAA 0x01A357 0x12 0x34 0x34 0x01A358 0x55 0x00A356 0x34 0x34 0x00A357
Before Instruction
TABLAT TBLPTR MEMORY(0x00A356)
After Instruction
TABLAT TBLPTR
Example 2:
Before Instruction
TABLAT TBLPTR MEMORY(0x01A357) MEMORY(0x01A358)
Status Affected: None Encoding:
After Instruction
TABLAT TBLPTR
Description:
This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2 Q2
No operation No operation (Read Program Memory)
Words: Cycles:
Q Cycle Activity: Q1
Decode No operation
Q3
No operation No operation
Q4
No operation No operation (Write TABLAT)
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TBLWT Syntax: Operands: Operation: Table Write [ label ] TBLWT ( *; *+; *-; +*) None if TBLWT*, (TABLAT) Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) - 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register;
0000 0000 0000 11nn nn = 0* = 1*+ = 2*= 3+*
TBLWT Words: 1 Cycles: 2 Q Cycle Activity: Q1
Decode No operation
Table Write (Continued)
Q2
No operation No operation (Read TABLAT)
Q3
No operation No operation
Q4
No operation No operation (Write to Holding Register)
Example 1:
TBLWT *+;
= = = = = = 0x55 0x00A356 0xFF 0x55 0x00A357 0x55
Status Affected: None Encoding:
Before Instruction
TABLAT TBLPTR HOLDING REGISTER (0x00A356) TABLAT TBLPTR HOLDING REGISTER (0x00A356)
After Instructions (table write completion)
Description:
This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 "Flash Program Memory" for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0:Least Significant Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment
Example 2:
TBLWT +*;
= = = = = = = = 0x34 0x01389A 0xFF 0xFF 0x34 0x01389B 0xFF 0x34
Before Instruction
TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B) TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B)
After Instruction (table write completion)
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TSTFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Test f, skip if 0 [ label ] TSTFSZ f [,a] 0 f 255 a [0,1] skip if f = 0 None
0110 011a ffff ffff
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k W N, Z
0000 1010 kkkk kkkk
If `f' = 0, the next instruction, fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
The contents of W are XOR'ed with the 8-bit literal `k'. The result is placed in W. 1 1 Q2
Read literal `k'
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to W
Words: Cycles:
Example:
W W = =
XORLW 0xAF
0xB5 0x1A
Before Instruction After Instruction
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NZERO ZERO = = = = No operation No operation TSTFSZ CNT : : Address (HERE) 0x00, Address (ZERO) 0x00, Address (NZERO)
Q4
No operation No operation
Example:
Before Instruction
PC
After Instruction
If CNT PC If CNT PC
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XORWF Syntax: Operands: Exclusive OR W with f [ label ] XORWF 0 f 255 d [0,1] a [0,1] (W) .XOR. (f) dest N, Z
0001 10da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' XORWF = = = = 0xAF 0xB5 0x1A 0xB5
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG
Q4
Write to destination
Example:
REG W REG W
Before Instruction
After Instruction
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21.0 DEVELOPMENT SUPPORT
21.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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21.2 MPASM Assembler 21.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
21.6 21.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 family of microcontrollers and the dsPIC30, dsPIC33 and PIC24 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
21.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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21.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 21.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
21.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
21.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC(R) and MCU devices. It debugs and programs PIC(R) and dsPIC(R) Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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21.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
21.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
21.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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22.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin, rather than pulling this pin directly to VSS.
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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PIC18F1220/1320
FIGURE 22-1: PIC18F1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V PIC18F1X20 4.2V
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
40 MHz
Frequency
FIGURE 22-2:
PIC18LF1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V PIC18LF1X20 4.2V
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
4 MHz
40 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC(R) device in the application.
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PIC18F1220/1320
FIGURE 22-3: PIC18F1220/1320 VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0V 5.5V 5.0V PIC18F1X20-E 4.2V
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
25 MHz
Frequency
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PIC18F1220/1320
22.1 DC Characteristics: Supply Voltage PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Supply Voltage PIC18LF1220/1320 PIC18F1220/1320 D002 D003 D004 VDR VPOR SVDD VBOR D005D RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage PIC18LF1220/1320 Industrial Low Voltage (-10C to +85C) BORV1:BORV0 = 11 BORV1:BORV0 = 10 BORV1:BORV0 = 01 BORV1:BORV0 = 00 D005F BORV1:BORV0 = 11 BORV1:BORV0 = 10 BORV1:BORV0 = 01 BORV1:BORV0 = 00 D005G BORV1:BORV0 = 1x BORV1:BORV0 = 01 BORV1:BORV0 = 00 D005H BORV1:BORV0 = 1x BORV1:BORV0 = 01 BORV1:BORV0 = 00 D005J BORV1:BORV0 = 1x BORV1:BORV0 = 01 BORV1:BORV0 = 00 D005K BORV1:BORV0 = 1x BORV1:BORV0 = 01 BORV1:BORV0 = 00 Legend: Note 1: 2: 3: N/A 2.50 3.88 4.18 N/A 2.34 3.63 3.90 N/A 3.88 4.18 N/A N/A 3.90 N/A 3.88 4.18 N/A N/A 3.90 N/A 2.72 4.22 4.54 N/A 2.72 4.22 4.54 N/A 4.22 4.54 N/A N/A 4.54 N/A 4.22 4.54 N/A N/A 4.54 N/A 2.94 4.56 4.90 N/A 3.10 4.81 5.18 N/A 4.56 4.90 N/A N/A 5.18 N/A 4.56 4.90 N/A N/A 5.18 V V V V V V V V V V V V V V V V V V V V (Note 2) (Note 2) Reserved (Note 2) (Note 2) Reserved Reserved (Note 2) Reserved (Note 3) (Note 3) Reserved Reserved (Note 3) (Note 2) (Note 2) Reserved Reserved 2.0 4.2 1.5 -- 0.05 -- -- -- -- -- 5.5 5.5 -- 0.7 -- V V V V See Section 4.1 "Power-on Reset (POR)" for details. HS, XT, RC and LP Oscillator mode Min Typ Max Units Conditions
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. Symbol VDD D001
V/ms See Section 4.1 "Power-on Reset (POR)" for details.
PIC18LF1220/1320 Industrial Low Voltage (-40C to -10C)
PIC18F1220/1320 Industrial (-10C to +85C)
PIC18F1220/1320 Industrial (-40C to -10C)
PIC18F1220/1320 Extended (-10C to +85C)
PIC18F1220/1320 Extended (-40C to -10C, +85C to +125C)
Shading of rows is to assist in readability of the table. This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 40 MHz for any VDD at which the BOR allows execution (low-voltage and industrial devices only). When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 25 MHz for any VDD at which the BOR allows execution (extended devices only).
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22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. Device
Power-Down Current (IPD)(1) PIC18LF1220/1320 0.1 0.1 0.2 PIC18LF1220/1320 0.1 0.1 0.3 All devices 0.1 0.1 0.4 Extended devices Supply Current (IDD)
(2,3)
0.5 0.5 1.9 0.5 0.5 1.9 2.0 2.0 6.5 50 40 40 40 68 68 68 80 80 80 80
A A A A A A A A A A A A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C
-40C +25C +85C -40C + 25C +85C -40C +25C +85C +125C VDD = 5.0V, (Sleep mode) VDD = 3.0V, (Sleep mode) VDD = 2.0V, (Sleep mode)
11.2 8 9 11
PIC18LF1220/1320
VDD = 2.0V
PIC18LF1220/1320
25 25 20
VDD = 3.0V
FOSC = 31 kHz (RC_RUN mode, Internal oscillator source)
All devices
55 55 50
VDD = 5.0V
Extended devices Legend: Note 1:
50
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
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PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF1220/1320
140 145 155
220 220 220 330 330 330 550 550 550 650 600 600 600 900 900 900 1.8 1.8 1.8 1.8
A A A A A A A A A A A A A A A A mA mA mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (RC_RUN mode, Internal oscillator source) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (RC_RUN mode, Internal oscillator source) VDD = 2.0V
PIC18LF1220/1320
215 225 235
All devices
385 390 405
Extended devices PIC18LF1220/1320
410 410 425 435
PIC18LF1220/1320
650 670 680
All devices
1.2 1.2 1.2
Extended devices Legend: Note 1:
1.2
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
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22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF1220/1320
4.7 5.0 5.8
8 8 11 11 11 15 16 16 22 75 150 150 150 180 180 180 380 380 380 435
A A A A A A A A A A A A A A A A A A A A
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (RC_IDLE mode, Internal oscillator source) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 31 kHz (RC_IDLE mode, Internal oscillator source) VDD = 2.0V
PIC18LF1220/1320
7.0 7.8 8.7
All devices
12 14 14
Extended devices PIC18LF1220/1320
25 75 85 95
PIC18LF1220/1320
110 125 135
All devices
180 195 200
Extended devices Legend: Note 1:
350
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
(c) 2007 Microchip Technology Inc.
DS39605F-page 243
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF1220/1320
140 140 150
275 275 275 375 375 375 800 800 800 800 250 250 250 350 350 350 1.0 1.0 1.0 1.0
A A A A A A A A A A A A A A A A mA mA mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V VDD = 3.0V FOSC = 1 MHZ (PRI_RUN mode, EC oscillator) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (RC_IDLE mode, Internal oscillator source) VDD = 2.0V
PIC18LF1220/1320
220 220 220
All devices
390 400 380
Extended devices PIC18LF1220/1320
410 150 150 160
PIC18LF1220/1320
340 300 280
All devices
0.72 0.63 0.58
Extended devices Legend: Note 1:
0.53
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
DS39605F-page 244
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF1220/1320
415 425 435
600 600 600 1.0 1.0 1.0 2.0 2.0 2.0 2.0 9.0 10.0 12 12 12 15 15 15
A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C +125C +125C -40C +25C +85C -40C +25C +85C VDD = 5.0V VDD = 4.2V FOSC = 40 MHZ (PRI_RUN mode, EC oscillator) VDD = 4.2V VDD = 5.0V FOSC = 25 MHz (PRI_RUN mode, EC oscillator) VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (PRI_RUN mode, EC oscillator) VDD = 2.0V
PIC18LF1220/1320
0.87 0.75 0.75
All devices
1.6 1.6 1.5
Extended devices Extended devices
1.5 6.3 9.7
All devices
9.4 9.5 9.6
All devices
11.9 12.1 12.2
Legend: Note 1:
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
(c) 2007 Microchip Technology Inc.
DS39605F-page 245
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF1220/1320
35 35 35
50 50 60 80 80 100 150 150 150 300 180 180 180 280 280 280 525 525 525 800 3.0 3.5
A A A A A A A A A A A A A A A A A A A A mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C +125C +125C VDD = 4.2V VDD = 5.0V FOSC = 25 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) VDD = 2.0V
PIC18LF1220/1320
55 50 60
All devices
105 110 115
Extended devices PIC18LF1220/1320
125 135 140 140
PIC18LF1220/1320
215 225 230
All devices
410 420 430
Extended devices Extended devices
450 2.2 2.7
Legend: Note 1:
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
DS39605F-page 246
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) All devices
3.2 3.2 3.3
4.1 4.1 4.1 5.1 5.1 5.1 9 9 11 12 12 14 20 20 25
mA mA mA mA mA mA A A A A A A A A A
-40C +25C +85C -40C +25C +85C -10C +25C +70C -10C +25C +70C -10C +25C +70C VDD = 5.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_RUN mode, Timer1 as clock) VDD = 2.0V VDD = 5.0V VDD = 4.2 V FOSC = 40 MHz (PRI_IDLE mode, EC oscillator)
All devices
4.0 4.1 4.1
PIC18LF1220/1320
5.1 5.8 7.9
PIC18LF1220/1320
7.9 8.9 10.5
All devices
12.5 16.3 18.4
Legend: Note 1:
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
(c) 2007 Microchip Technology Inc.
DS39605F-page 247
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF1220/1320
9.2 9.6 12.7
15 15 18 30 30 35 80 80 80
A A A A A A A A A
-10C +25C +70C -10C +25C +70C -10C +25C +70C VDD = 5.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_IDLE mode, Timer1 as clock) VDD = 2.0V
PIC18LF1220/1320
22 21 20
All devices
50 45 45
Legend: Note 1:
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
DS39605F-page 248
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. Device
Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) D022 (IWDT) Watchdog Timer 1.5 2.2 3.1 2.5 3.3 4.7 3.7 4.5 6.1 D022A (IBOR) D022B (ILVD) Brown-out Reset Low-Voltage Detect 19 24 8.5 16 20 D025 (IOSCB) Timer1 Oscillator 1.7 1.8 2.1 2.2 2.6 2.8 3.0 3.3 3.6 D026 (IAD) A/D Converter 1.0 1.0 2.0 1.0 Legend: Note 1: 4.0 4.0 5.0 6.0 6.0 7.0 10.0 10.0 13.0 35.0 45.0 25.0 35.0 45.0 3.5 3.5 4.5 4.5 4.5 5.5 6.0 6.0 7.0 3.0 4.0 10.0 8.0 A A A A A A A A A A A A A A A A A A A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C to +85C -40C to +85C -40C to +85C -40C to +125C VDD = 2.0V VDD = 3.0V VDD = 5.0V VDD = 5.0V A/D on, not converting VDD = 5.0V 32 kHz on Timer1(4) VDD = 3.0V 32 kHz on Timer1(4) VDD = 2.0V 32 kHz on Timer1(4) VDD = 3.0V VDD = 5.0V VDD = 2.0V VDD = 3.0V VDD = 5.0V VDD = 5.0V VDD = 3.0V VDD = 2.0V
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
(c) 2007 Microchip Technology Inc.
DS39605F-page 249
PIC18F1220/1320
22.3 DC Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Input Low Voltage I/O ports: D030 D030A D031 D032 D032A D033 VIH D040 D040A D041 D042 D042A D043 IIL D060 D061 D063 IPU D070 Note 1: 2: IPURB with Schmitt Trigger buffer MCLR, OSC1 (EC mode) OSC1 (in XT, HS and LP modes) and T1OSI OSC1 (RC mode)(1) Input Leakage Current(2,3) I/O ports MCLR OSC1 Weak Pull-up Current PORTB weak pull-up current 50 400 A VDD = 5V, VPIN = VSS -- -- -- 1 5 5 A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD with Schmitt Trigger buffer MCLR OSC1 (in XT, HS and LP modes) and T1OSI OSC1 (in RC and EC mode)(1) Input High Voltage I/O ports: with TTL buffer 0.25 VDD + 0.8V 2.0 0.8 VDD 0.8 VDD 1.6 VDD 0.9 VDD VDD VDD VDD VDD VDD VDD V V V V V V VDD < 4.5V 4.5V VDD 5.5V with TTL buffer VSS -- VSS VSS VSS VSS 0.15 VDD 0.8 0.2 VDD 0.2 VDD 0.3 VDD 0.2 VDD V V V V V V VDD < 4.5V 4.5V VDD 5.5V Min Max Units Conditions
DC CHARACTERISTICS Param Symbol No. VIL
3: 4:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested.
DS39605F-page 250
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
22.3 DC Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Output Low Voltage I/O ports OSC2/CLKO (RC mode) VOH D090 D092 D150 VOD Output High Voltage(3) I/O ports OSC2/CLKO (RC mode) Open-Drain High Voltage Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin
--
DC CHARACTERISTICS Param Symbol No. VOL D080 D083
Min
Max
Units
Conditions
-- --
0.6 0.6
V V
IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C RA4 pin
VDD - 0.7 VDD - 0.7 --
-- -- 8.5
V V V
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1 To meet the AC timing specifications In I2C mode
D101 D102 Note 1: 2:
CIO CB
All I/O pins and OSC2 (in RC mode) SCL, SDA
-- --
50 400
pF pF
3: 4:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested.
(c) 2007 Microchip Technology Inc.
DS39605F-page 251
PIC18F1220/1320
TABLE 22-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Internal Program Memory Programming Specifications(1) D110 D112 D113 VPP IPP IDDP Voltage on MCLR/VPP pin Current into MCLR/VPP pin Supply Current during Programming Data EEPROM Memory D120 D121 ED VDRW Byte Endurance VDD for Read/Write 100K VMIN 1M -- -- 5.5 E/W -40C to +85C V Using EECON to read/write VMIN = Minimum operating voltage 9.00 -- -- -- -- -- 13.25 5 10 V A mA (Note 2) Min Typ Max Units Conditions DC CHARACTERISTICS Param No. Sym
D122 D123 D124
TDEW
Erase/Write Cycle Time
-- 40 1M
4 -- 10M
-- -- --
ms Year Provided no other specifications are violated E/W -40C to +85C
TRETD Characteristic Retention TREF Number of Total Erase/Write Cycles before Refresh(3) Program Flash Memory Cell Endurance VDD for Read VDD for Block Erase VDD for Externally Timed Erase or Write VDD for Self-Timed Write ICSPTM Block Erase Cycle Time ICSP Erase or Write Cycle Time (externally timed) Self-Timed Write Cycle Time
D130 D131 D132
EP VPR VIE
10K VMIN 4.5 4.5 VMIN -- 1 -- 40
100K -- -- -- -- 4 -- 2 --
-- 5.5 5.5 5.5 5.5 -- -- -- --
E/W -40C to +85C V V V V ms ms ms Year Provided no other specifications are violated VMIN = Minimum operating voltage Using ICSP port Using ICSP port VMIN = Minimum operating voltage VDD > 4.5V VDD > 4.5V
D132A VIW D132B VPEW D133 TIE
D133A TIW D133A TIW D134
TRETD Characteristic Retention
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: The pin may be kept in this range at times other than programming, but it is not recommended. 3: Refer to Section 7.8 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance.
DS39605F-page 252
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 22-4: LOW-VOLTAGE DETECT CHARACTERISTICS
VDD (LVDIF can be cleared in software)
VLVD (LVDIF set by hardware)
LVDIF
TABLE 22-2:
PIC18LF1220/1320 (Industrial)
LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic LVD Voltage on VDD Transition High-to-Low PIC18LF1220/1320 LVDL<3:0> = 0000 LVDL<3:0> = 0001 LVDL<3:0> = 0010 LVDL<3:0> = 0011 LVDL<3:0> = 0100 LVDL<3:0> = 0101 LVDL<3:0> = 0110 LVDL<3:0> = 0111 LVDL<3:0> = 1000 LVDL<3:0> = 1001 LVDL<3:0> = 1010 LVDL<3:0> = 1011 LVDL<3:0> = 1100 LVDL<3:0> = 1101 LVDL<3:0> = 1110 Min Typ Max Units Conditions
PIC18F1220/1320 (Industrial, Extended) Param No. D420D Symbol
Industrial Low Voltage (-10C to +85C) N/A N/A 2.08 2.26 2.35 2.55 2.64 2.82 3.09 3.29 3.38 3.56 3.75 3.93 4.23 N/A N/A 2.26 2.45 2.55 2.77 2.87 3.07 3.36 3.57 3.67 3.87 4.07 4.28 4.60 N/A N/A 2.44 2.65 2.76 2.99 3.10 3.31 3.63 3.86 3.96 4.18 4.40 4.62 4.96 V V V V V V V V V V V V V V V Reserved Reserved
Legend:
Shading of rows is to assist in readability of the table. Production tested at TAMB = 25C. Specifications over temperature limits ensured by characterization.
(c) 2007 Microchip Technology Inc.
DS39605F-page 253
PIC18F1220/1320
TABLE 22-2:
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial, Extended) Param No. D420F Symbol Characteristic LVD Voltage on VDD Transition High-to-Low PIC18LF1220/1320 LVDL<3:0> = 0000 LVDL<3:0> = 0001 LVDL<3:0> = 0010 LVDL<3:0> = 0011 LVDL<3:0> = 0100 LVDL<3:0> = 0101 LVDL<3:0> = 0110 LVDL<3:0> = 0111 LVDL<3:0> = 1000 LVDL<3:0> = 1001 LVDL<3:0> = 1010 LVDL<3:0> = 1011 LVDL<3:0> = 1100 LVDL<3:0> = 1101 LVDL<3:0> = 1110 LVD Voltage on VDD Transition High-to-Low D420G PIC18F1220/1320 LVDL<3:0> = 1101 LVDL<3:0> = 1110 LVD Voltage on VDD Transition High-to-Low D420H PIC18F1220/1320 LVDL<3:0> = 1101 LVDL<3:0> = 1110 LVD Voltage on VDD Transition High-to-Low D420J PIC18F1220/1320 LVDL<3:0> = 1101 LVDL<3:0> = 1110 LVD Voltage on VDD Transition High-to-Low D420K PIC18F1220/1320 LVDL<3:0> = 1101 LVDL<3:0> = 1110 Legend:
LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
Industrial Low Voltage (-40C to -10C) N/A N/A 1.99 2.16 2.25 2.43 2.53 2.70 2.96 3.14 3.23 3.41 3.58 3.76 4.04 3.93 4.23 3.76 4.04 3.94 4.23 3.77 4.05 N/A N/A 2.26 2.45 2.55 2.77 2.87 3.07 3.36 3.57 3.67 3.87 4.07 4.28 4.60 4.28 4.60 4.28 4.60 4.28 4.60 4.28 4.60 N/A N/A 2.53 2.75 2.86 3.10 3.21 3.43 3.77 4.00 4.11 4.34 4.56 4.79 5.15 4.62 4.96 4.79 5.15 4.62 4.96 4.79 5.15 V V V V V V V V V V V V V V V V V V V V V V V Reserved Reserved
Industrial (-10C to +85C)
Industrial (-40C to -10C)
Extended (-10C to +85C)
Extended (-40C to -10C, +85C to +125C)
Shading of rows is to assist in readability of the table. Production tested at TAMB = 25C. Specifications over temperature limits ensured by characterization.
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22.4
22.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-Impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition 3. TCC:ST 4. Ts T (I2C specifications only) (I2C specifications only) Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T13CKI WR
P R V Z High Low
Period Rise Valid High-Impedance High Low
SU STO
Setup Stop condition
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22.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 22-3 apply to all timing specifications unless otherwise noted. Figure 22-5 specifies the load conditions for the timing specifications.
TABLE 22-3:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 22.1 and Section 22.3. LF parts operate for industrial temperatures only.
AC CHARACTERISTICS
FIGURE 22-5:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 VDD/2 CL VSS pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2/CLKO Load Condition 2
RL
Pin
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22.4.3 TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 22-6:
OSC1
1 2 3 3 4 4
CLKO
TABLE 22-4:
Param. No. 1A
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKI Frequency(1) Oscillator Frequency(1) Min DC DC DC DC DC 1 DC Max 40 25 4 1 25 10 33 -- -- -- -- -- 1000 -- -- -- -- -- 20 50 7.5 Units MHz MHz MHz MHz MHz MHz kHz ns ns ns ns ns ns s ns ns s ns ns ns ns Conditions EC, ECIO (LF and Industrial) EC, ECIO (Extended) RC oscillator XT oscillator HS oscillator HS + PLL oscillator LP Oscillator mode EC, ECIO (LF and Industrial) EC, ECIO (Extended) RC oscillator XT oscillator HS oscillator HS + PLL oscillator LP oscillator TCY = 4/FOSC XT oscillator LP oscillator HS oscillator XT oscillator LP oscillator HS oscillator
Symbol FOSC
1
TOSC
External CLKI Period(1) Oscillator Period(1)
25 40 250 1000 25 100 30
2 3
TCY TosL, TosH
Instruction Cycle
Time(1)
100 30 2.5 10 -- -- --
External Clock in (OSC1) High or Low Time
4
TosR, TosF
External Clock in (OSC1) Rise or Fall Time
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
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TABLE 22-5:
Param No. F10 F11 F12 F13 Sym
PLL CLOCK TIMING SPECIFICATIONS, HS/HSPLL MODE (VDD = 4.2V TO 5.5V)
Characteristic Min 4 16 -- -2 Typ -- -- -- -- Max 10 40 2 +2 Units MHz MHz ms % Conditions HS and HSPLL mode only HSPLL mode only HSPLL mode only HSPLL mode only
FOSC Oscillator Frequency Range FSYS TPLL CLK On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Jitter)
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 22-6:
PIC18LF1220/1320 (Industrial) PIC18F1220/1320 (Industrial) Param No.
INTERNAL RC ACCURACY: PIC18F1220/1320 (INDUSTRIAL) PIC18LF1220/1320 (INDUSTRIAL)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Device Min Typ Max Units Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) PIC18LF1220/1320 -2 -5 -10 PIC18F1220/1320PIC18F 1220/1320 -2 -5 -10 INTRC Accuracy @ Freq = 31 kHz PIC18LF1220/1320
(2)
+/-1 -- -- +/-1 -- -- -- --
2 5 10 2 5 10 35.938 35.938
% % % % % % kHz kHz
+25C
VDD = 2.7-3.3V
-10C to +85C VDD = 2.7-3.3V -40C to +85C VDD = 2.7-3.3V +25C VDD = 4.5-5.5V -10C to +85C VDD = 4.5-5.5V -40C to +85C VDD = 4.5-5.5V -40C to +85C VDD = 2.7-3.3V -40C to +85C VDD = 4.5-5.5V
26.562
PIC18F1220/1320PIC18F 26.562 1220/1320 Legend: Note 1: 2: 3:
Shading of rows is to assist in readability of the table. Frequency calibrated at 25C. OSCTUNE register can be used to compensate for temperature and VDD drift. INTRC frequency after calibration. Change of INTRC frequency as VDD changes.
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PIC18F1220/1320
FIGURE 22-7: CLKO AND I/O TIMING
Q4 OSC1 10 CLKO 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 Note: Refer to Figure 22-5 for load conditions. 15 New Value 19 18 12 16 11 Q1 Q2 Q3
TABLE 22-7:
Param. Symbol No. 10 11 12 13 14 15 16 17 18 18A 19 20 20A 21 21A Note 1: TioF
CLKO AND I/O TIMING REQUIREMENTS
Characteristic Min -- -- -- -- -- 0.25 TCY + 25 0 -- 100 200 0 PIC18F1X20 PIC18LF1X20 Port Output Fall Time PIC18F1X20 PIC18LF1X20 -- -- -- -- Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- Max 200 200 100 100 0.5 TCY + 20 -- -- 150 -- -- -- 25 60 25 60 Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckL OSC1 to CLKO TosH2ckH OSC1 to CLKO TckR TckF TckL2ioV TckH2ioI TosH2ioI CLKO Rise Time CLKO Fall Time CLKO to Port Out Valid Port In Hold after CLKO OSC1 (Q2 cycle) to Port PIC18F1X20 Input Invalid (I/O in hold time) PIC18LF1X20
TioV2ckH Port In Valid before CLKO TosH2ioV OSC1 (Q1 cycle) to Port Out Valid
TioV2osH Port Input Valid to OSC1 (I/O in setup time) TioR Port Output Rise Time
Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
FIGURE 22-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O pins Note: Refer to Figure 22-5 for load conditions. 32 30
31
34
FIGURE 22-9:
BROWN-OUT RESET TIMING
BVDD VDD 35 VBGAP = 1.2V
VIRVST
Enable Internal Reference Voltage Internal Reference Voltage Stable 36
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TABLE 22-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS
Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No postscaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-Impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Time for Internal Reference Voltage to become stable Low-Voltage Detect Pulse Width Min 2 3.48 1024 TOSC -- -- 200 -- 200 Typ -- 4.00 -- 65.5 2 -- 20 -- Max -- 4.71 1024 TOSC 132 -- -- 50 -- Units s ms -- ms s s s s VDD VLVD VDD BVDD (see D005) TOSC = OSC1 period Conditions Param. Symbol No. 30 31 32 33 34 35 36 37 TmcL TWDT TOST TPWRT TIOZ TBOR TIVRST TLVD
FIGURE 22-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42 T1OSO/T13CKI
45
46
47 TMR0 or TMR1 Note: Refer to Figure 22-5 for load conditions.
48
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TABLE 22-9:
Param Symbol No. 40 41 42 Tt0H Tt0L Tt0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No prescaler With prescaler No prescaler With prescaler No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 10 Greater of: 20 ns or TCY + 40 N 0.5 TCY + 20 10 25 30 50 0.5 TCY + 5 10 25 30 50 Greater of: 20 ns or TCY + 40 N 60 DC 2 TOSC Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (1, 2, 4,..., 256) Conditions
45
Tt1H
T13CKI High Time Synchronous, no prescaler Synchronous, PIC18F1X20 with prescaler PIC18LF1X20 Asynchronous PIC18F1X20 PIC18LF1X20
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46
Tt1L
T13CKI Low Time Synchronous, no prescaler Synchronous, PIC18F1X20 with prescaler PIC18LF1X20 Asynchronous PIC18F1X20 PIC18LF1X20
47
Tt1P
T13CKI Input Period
Synchronous
Asynchronous Ft1 48 T13CKI Oscillator Input Frequency Range Tcke2tmrI Delay from External T13CKI Clock Edge to Timer Increment
-- 50 7 TOSC
ns kHz --
FIGURE 22-11:
CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx (Capture Mode)
50 52
51
CCPx (Compare or PWM Mode) 53 54
Note:
Refer to Figure 22-5 for load conditions.
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PIC18F1220/1320
TABLE 22-10: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param. Symbol No. 50 TccL Characteristic CCPx Input Low No prescaler Time With prescaler PIC18F1X20 PIC18LF1X20 51 TccH CCPx Input High No prescaler Time With prescaler PIC18F1X20 PIC18LF1X20 52 53 54 TccP TccR TccF CCPx Input Period CCPx Output Fall Time CCPx Output Fall Time PIC18F1X20 PIC18LF1X20 PIC18F1X20 PIC18LF1X20 Min 0.5 TCY + 20 10 20 0.5 TCY + 20 10 20 3 TCY + 40 N -- -- -- -- Max -- -- -- -- -- -- -- 25 45 25 45 Units ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions
FIGURE 22-12:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RB1/AN5/TX/ CK/INT1 pin RB4/AN6/RX/ DT/KBI0 pin 120 Note:
121
121
122
Refer to Figure 22-5 for load conditions.
TABLE 22-11: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param. Symbol No. 120 Characteristic Min Max Units Conditions
TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid Tckrf Tdtrf Clock Out Rise Time and Fall Time (Master mode) Data Out Rise Time and Fall Time
PIC18F1X20 PIC18LF1X20 PIC18F1X20 PIC18LF1X20 PIC18F1X20 PIC18LF1X20
-- -- -- -- -- --
40 100 20 50 20 50
ns ns ns ns ns ns
121 122
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
FIGURE 22-13:
RB1/AN5/TX/ CK/INT1 pin RB4/AN6/RX/ DT/KBI0 pin 126 Note: Refer to Figure 22-5 for load conditions.
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
TABLE 22-12: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param. No. 125 126 Symbol TdtV2ckl TckL2dtl Characteristic SYNC RCV (MASTER & SLAVE) Data Hold before CK (DT hold time) Data Hold after CK (DT hold time) Min Max Units Conditions
10 15
-- --
ns ns
TABLE 22-13: A/D CONVERTER CHARACTERISTICS: PIC18F1220/1320 (INDUSTRIAL) PIC18LF1220/1320 (INDUSTRIAL)
Param Symbol No. A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A28 A29 A30 A40 NR EIL EDL EOFF EGN -- VREF VREFH VREFL VAIN AVDD AVSS ZAIN IAD Characteristic Resolution Integral Linearity Error Differential Linearity Error Offset Error Gain Error Monotonicity Reference Voltage Range (VREFH - VREFL) Reference Voltage High Reference Voltage Low Analog Input Voltage Analog Supply Voltage Analog Supply Voltage Recommended Impedance of Analog Voltage Source A/D Conversion PIC18F1X20 Current (VDD) PIC18LF1X20 VREF Input Current (Note 3) 3 AVSS + 3.0V AVSS - 0.3V VREFL VDD - 0.3 VSS - 0.3 -- -- -- -- -- Min -- -- -- -- -- Typ -- -- -- -- -- guaranteed(2) -- -- -- -- -- -- -- 180 90 -- -- AVDD - AVSS AVDD + 0.3V AVDD - 3.0V VREFH VDD + 0.3 VSS + 0.3 2.5 -- -- 5 150 Max 10 <1 <1 <1 <1 Units bit Conditions VREF 3.0V
LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V -- V V V V V V k A A A A Average current consumption when A/D is on (Note 1) During VAIN acquisition. During A/D conversion cycle. For 10-bit resolution For 10-bit resolution For 10-bit resolution
A50
IREF
Note 1: 2: 3:
When A/D is off, it will not consume any current other than minor leakage current. The power-down current specification includes any such leakage from the A/D module. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source.
DS39605F-page 264
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PIC18F1220/1320
FIGURE 22-14: A/D CONVERSION TIMING
BSF ADCON0, GO (Note 2) Q4 130 A/D CLK(1) 132 131
A/D DATA
9
8
7
...
...
2
1
0
ADRES
OLD_DATA
NEW_DATA TCY
ADIF GO Sampling Stopped DONE
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 22-14: A/D CONVERSION REQUIREMENTS
Param Symbol No. 130 TAD Characteristic A/D Clock Period PIC18F1X20 PIC18LF1X20 PIC18F1X20 PIC18LF1X20 131 132 135 136 TCNV TACQ TSWC TAMP Conversion Time (not including acquisition time) (Note 1) Acquisition Time (Note 3) Switching Time from Convert Sample Amplifier Settling Time (Note 2) Min 1.6 3.0 2.0 3.0 11 15 10 -- 1 Max 20(5) 20(5) 6.0 9.0 12 -- -- (Note 4) -- s This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Units s s s s TAD s s -40C Temp +125C 0C Temp +125C Conditions TOSC based, VREF 3.0V TOSC based, VREF full range A/D RC mode A/D RC mode
Note 1: 2: 3: 4: 5:
ADRES register may be read on the following TCY cycle. See Section 17.0 "10-Bit Analog-to-Digital Converter (A/D) Module" for minimum conditions when input voltage has changed more than 1 LSb. The time for the holding capacitor to acquire the "New" input voltage, when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50. On the next Q4 cycle of the device clock. The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
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NOTES:
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23.0
Note:
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 23-1:
0.5
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25C
0.4
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
5.0V 0.3 IDD (mA) 4.5V
4.0V 0.2 3.5V 3.0V
0.1
2.5V 2.0V
0.0 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
FIGURE 23-2:
0.7
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40C TO +85C
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V
0.6
0.5
4.5V 0.4 IDD (mA) 4.0V 0.3 3.5V 3.0V 0.2 2.5V 0.1 2.0V 0.0 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
FIGURE 23-3:
0.7
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40C TO +125C
0.6
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V
0.5
4.5V 0.4 IDD (mA) 4.0V 0.3 3.5V 3.0V 0.2 2.5V 0.1 2.0V
0.0 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
FIGURE 23-4:
2.0
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25C
1.8
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
1.6 5.5V 1.4 5.0V 1.2 IDD (mA) 4.5V 1.0 4.0V 3.5V 3.0V 0.6 2.5V 0.4 2.0V
0.8
0.2
0.0 1.0 1.5 2.0 2.5 FOSC (MHz) 3.0 3.5 4.0
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FIGURE 23-5:
2.5
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40C TO +125C
2.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V 1.5 IDD (mA) 4.5V 4.0V 1.0 3.5V 3.0V 2.5V 0.5 2.0V
0.0 1.0 1.5 2.0 2.5 FOSC (MHz) 3.0 3.5 4.0
FIGURE 23-6:
16
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25C
14
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
12 5.0V 10 4.5V IDD (mA) 8 4.0V 6 3.5V 4 3.0V 2 2.5V 2.0V 0 4 8 12 16 20 FOSC (MHz) 24 28 32 36 40
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FIGURE 23-7:
16
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40C TO +125C
14
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V
12 4.0V 10 4.5V IDD (mA) 8
6
3.5V
4 3.0V 2 2.5V 2.0V 0 4 8 12 16 20 FOSC (MHz) 24 28 32 36 40
FIGURE 23-8:
0.035
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25C
0.030
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
5.0V 0.025 4.5V
0.020 IDD (mA)
4.0V 3.5V
0.015 3.0V 2.5V 2.0V
0.010
0.005
0.000 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
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FIGURE 23-9:
0.045
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40C TO +85C
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
0.040
0.035 5.0V 0.030 4.5V IDD (mA) 0.025 4.0V 0.020 3.5V 0.015 3.0V 2.5V 0.010 2.0V
0.005
0.000 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
FIGURE 23-10:
0.100
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40C TO +125C
0.090
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
0.080 5.0V
0.070
0.060 IDD (mA)
4.5V 4.0V 3.5V 3.0V
0.050
0.040
0.030 2.5V 0.020 2.0V
0.010
0.000 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
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PIC18F1220/1320
FIGURE 23-11:
600
TYPICAL IDD vs. FOSC OVERVVDD PRI_IDLE, EC MODE, +25C Typical I vs F over PRI_IDLE, EC mode, +25C
500
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V
400 4.5V IDD (A) 4.0V 3.5V 3.0V 200 2.5V 2.0V 100
300
0 1.0 1.5 2.0 2.5 FOSC (MHz) 3.0 3.5 4.0
FIGURE 23-12:
600
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40C TO +125C
500
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
5.0V 400 4.5V 4.0V 300 3.5V
IDD (A)
3.0V 200 2.5V 2.0V 100
0 1.0 1.5 2.0 2.5 FOSC (MHz) 3.0 3.5 4.0
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PIC18F1220/1320
FIGURE 23-13:
6.0 5.5 5.0 4.5 5.5V 4.0 3.5 IDD (mA) 4.5V 3.0 4.0V 2.5 2.0 1.5 1.0 0.5 2.0V 0.0 4 8 12 16 20 FOSC (MHz) 24 28 32 36 40 2.5V 3.0V 5.0V
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25C
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
3.5V
FIGURE 23-14:
6.0 5.5 5.0 4.5 4.0 3.5 IDD (mA)
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40C TO +125C
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V 4.5V
4.0V 3.0 2.5 3.5V 2.0 1.5 1.0 0.5 2.0V 0.0 4 8 12 16 20 FOSC (MHz) 24 28 32 36 40 2.5V
3.0V
(c) 2007 Microchip Technology Inc.
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FIGURE 23-15:
3000
TYPICAL IPD vs. VDD (+25C), 125 kHz TO 8 MHz RC_RUN MODE, ALL PERIPHERALS DISABLED
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
2500
8 MHz 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves.
2000
IPD (A)
1500
4 MHz
1000
2 MHz
500
1 MHz 125 kHz
0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 23-16:
3500
MAXIMUM IPD vs. VDD (-40C TO +125C), 125 kHz TO 8 MHz RC_RUN MODE, ALL PERIPHERALS DISABLED
3000 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves.
8 MHz
2500
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
2000 IPD (A)
4 MHz 1500
1000
2 MHz
500
1 MHz 125 kHz
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 23-17:
100
TYPICAL AND MAXIMUM IPD vs. VDD (-40C TO +125C), 31.25 kHz RC_RUN MODE, ALL PERIPHERALS DISABLED
Max (+125C) Max (+85C) Typ (+25C) IPD (A)
10
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
1 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 23-18:
800 750 700 650 600 550 500
TYPICAL IPD vs. VDD (+25C), 125 kHz TO 8 MHz RC_IDLE MODE, ALL PERIPHERALS DISABLED
250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves.
8 MHz
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
4 MHz 2 MHz 1 MHz 125 kHz
IPD (A)
450 400 350 300 250 200 150 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
VDD (V)
(c) 2007 Microchip Technology Inc.
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FIGURE 23-19:
800 750 700 650 600 550 500 IPD (A) 450 400 350 300 250 200 150 100 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves. 8 MHz
MAXIMUM IPD vs. VDD (-40C TO +125C), 125 kHz TO 8 MHz RC_IDLE MODE, ALL PERIPHERALS DISABLED
4 MHz 2 MHz 1 MHz 125 kHz
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
FIGURE 23-20:
100
TYPICAL AND MAXIMUM IPD vs. VDD (-40C TO +125C), 31.25 kHz RC_IDLE MODE, ALL PERIPHERALS DISABLED
Max (+125C)
IPD (A)
Max (+85C) 10 Typ (+25C)
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
1 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 23-21:
80
IPD SEC_RUN MODE, -10C TO +70C, 32.768 kHz XTAL, 2 x 22 pF, ALL PERIPHERALS DISABLED
70
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
60 Max (+70C) 50
IPD (A)
40 Typ (+25C)
30
20
10
0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 23-22:
20
IPD SEC_IDLE MODE, -10C TO +70C, 32.768 kHz, 2 x 22 pF, ALL PERIPHERALS DISABLED
18
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
16
14 Max (+70C) 12
IPD (A)
10 Typ (+25C) 8
6
4
2
0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
FIGURE 23-23:
100 Max (+125C)
TOTAL IPD, -40C TO +125C SLEEP MODE, ALL PERIPHERALS DISABLED
10 Max (+85C)
1
IPD (A)
0.1
Typ (+25C) 0.01
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 23-24:
3.0
VOH vs. IOH OVER TEMPERATURE (-40C TO +125C), VDD = 3.0V
2.5
2.0 Max (+125C) VOH (V) 1.5 Typ (+25C) Min (+125C) 1.0
0.5
0.0 0 5 10 IOH (-mA) 15 20 25
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PIC18F1220/1320
FIGURE 23-25:
5.0
VOH vs. IOH OVER TEMPERATURE (-40C TO +125C), VDD = 5.0V
4.5 Max (+125C) 4.0 Typ (+25C) 3.5
3.0 VOH (V)
2.5 Min (+125C) 2.0
1.5
1.0
0.5
0.0 0 5 10 IOH (-mA) 15 20 25
FIGURE 23-26:
3.0
VOL vs. IOL OVER TEMPERATURE (-40C TO +125C), VDD = 3.0V V vs I over Temp (-40C to +125C) V = 3.0V
Max (+125C) 2.5
2.0
Max (+85C)
VOL (V)
1.5
Typ (+25C) 1.0
0.5 Min (+125C)
0.0 0 5 10 IOL (-mA) 15 20 25
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PIC18F1220/1320
FIGURE 23-27:
1.0
VOL vs. IOL OVER TEMPERATURE (-40C TO +125C), VDD = 5.0V
0.9 Max (+125C) 0.8
0.7
0.6 Max (+85C) VOL (V) 0.5
0.4 Typ (+25C) 0.3
0.2 Min (+125C) 0.1
0.0 0 5 10 IOL (-mA) 15 20 25
FIGURE 23-28:
IPD TIMER1 OSCILLATOR, -10C TO +70C SLEEP MODE, TMR1 COUNTER DISABLED SLEEP mode, TMR1 counter disabled IPD Timer1 Oscillator, -10C to +70C
5.0
4.5 Max (-10C to +70C) 4.0
3.5
3.0 Typ (+25C)
IPD (A)
2.5
2.0
1.5
1.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
0.5
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
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FIGURE 23-29:
4.5
IPD FSCM vs. VDD OVER TEMPERATURE PRI_IDLE MODE, EC OSCILLATOR AT 32 kHz, -40C TO +125C
4.0 Max (-40C) 3.5
3.0
IPD (A)
2.5 Typ (+25C) 2.0
1.5
1.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
0.5
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 23-30:
14
IPD WDT, -40C TO +125C SLEEP MODE, ALL PERIPHERALS DISABLED
12
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
10 Max (+125C)
IPD (A)
8
6 Max (+85C) 4 Typ (+25C)
2
0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
FIGURE 23-31:
50
IPD LVD vs. VDD SLEEP MODE, LVDL3:LVDL0 = 0001 (2V)
45
40
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
Max (+125C)
35 Max (+85C) 30 IPD (A) Typ (+25C)
25
20
15
10 Low-Voltage Detection Range 5 Normal Operating Range 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 23-32:
40
IPD BOR vs. VDD, -40C TO +125C SLEEP MODE, BORV1:BORV0 = 11 (2V)
35
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
Max (+125C)
30
25 Typ (+25C)
IPD (A)
20
15
10 Device may be in Reset 5 Device is Operating 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
DS39605F-page 282
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 23-33:
10
IPD A/D, -40C TO +125C SLEEP MODE, A/D ENABLED (NOT CONVERTING)
Max (+125C)
1
IPD (A)
Max (+85C) 0.1
0.01
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
Typ (+25C)
0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 23-34:
5.0
AVERAGE FOSC vs. VDD FOR VARIOUS R's EXTERNAL RC MODE, C = 20 pF, TEMPERATURE = +25C
Operation above 4 MHz is not recomended 4.5
4.0 5.1K 3.5
3.0 Freq (MHz)
2.5 10K 2.0
1.5
1.0 33K 0.5 100K 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
FIGURE 23-35:
2.0
AVERAGE FOSC vs. VDD FOR VARIOUS R's EXTERNAL RC MODE, C = 100 pF, TEMPERATURE = +25C
1.8
1.6 5.1K 1.4
1.2 Freq (MHz)
1.0 10K 0.8
0.6
0.4 33K 0.2 100K 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 23-36:
0.8
AVERAGE FOSC vs. VDD FOR VARIOUS R's EXTERNAL RC MODE, C = 300 pF, TEMPERATURE = +25C
0.7
0.6
0.5 Freq (MHz) 5.1K 0.4
0.3 10K 0.2
0.1
33K 100K
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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PIC18F1220/1320
24.0
24.1
PACKAGING INFORMATION
Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F1320-I/P e3 0710017
18-Lead SOIC
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC18F1220E/SO e3 0710017
20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example PIC18F1220E/SS e3 0710017
28-Lead QFN
Example
XXXXXXXX XXXXXXXX YYWWNNN
18F1320 -I/ML e3 0710017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
24.2 Package Details
The following sections give the technical details of the packages.
18-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N NOTE 1
E1
1
2
3 D E
A
A2 L A1 b1 b e
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .115 .015 .300 .240 .880 .115 .008 .045 .014 - MIN INCHES NOM 18 .100 BSC - .130 - .310 .250 .900 .130 .010 .060 .018 - .210 .195 - .325 .280 .920 .150 .014 .070 .022 MAX
c
eB
.430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-007B
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PIC18F1220/1320
18-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1 NOTE 1 1 23 b
e h A2 c h
A
A1
L L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.20 0.31 5 5 0.25 0.40 - 2.05 0.10 MIN
MILLIMETERS NOM 18 1.27 BSC - - - 10.30 BSC 7.50 BSC 11.55 BSC - - 1.40 REF - - - - - 8 0.33 0.51 15 0.75 1.27 2.65 - 0.30 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-051B
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
NOTE 1 12 b e
A
A2
c
A1 L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Lead Thickness Foot Angle Lead Width N e A A2 A1 E E1 D L L1 c b 0.09 0 0.22 - 1.65 0.05 7.40 5.00 6.90 0.55 MIN MILLIMETERS NOM 20 0.65 BSC - 1.75 - 7.80 5.30 7.20 0.75 1.25 REF - 4 - 0.25 8 0.38 2.00 1.85 - 8.20 5.60 7.50 0.95 MAX
L
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-072B
DS39605F-page 288
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PIC18F1220/1320
28-Lead Plastic Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN] with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D2
EXPOSED PAD
e E E2 2 1 N NOTE 1 TOP VIEW BOTTOM VIEW 2 1 N L K
b
A
A3
A1
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad N e A A1 A3 E E2 D D2 b L K 3.65 0.23 0.50 0.20 3.65 0.80 0.00 MIN MILLIMETERS NOM 28 0.65 BSC 0.90 0.02 0.20 REF 6.00 BSC 3.70 6.00 BSC 3.70 0.30 0.55 - 4.20 0.35 0.70 - 4.20 1.00 0.05 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-105B
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
NOTES:
DS39605F-page 290
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PIC18F1220/1320
APPENDIX A: REVISION HISTORY
Revision F (February 2007)
This revision includes updates to the packaging diagrams.
Revision A (August 2002)
Original data sheet for PIC18F1220/1320 devices.
Revision B (November 2002)
This revision includes significant changes to Section 2.0, Section 3.0 and Section 19.0, as well as updates to the Electrical Specifications in Section 22.0 and includes minor corrections to the data sheet text.
APPENDIX B:
DEVICE DIFFERENCES
The differences between the devices listed in this data sheet are shown in Table B-1.
Revision C (May 2004)
This revision includes updates to the Electrical Specifications in Section 22.0, the DC and AC Characteristics Graphs and Tables in Section 23.0 and includes minor corrections to the data sheet text.
Revision D (October 2006)
This revision includes updates to the packaging diagrams.
Revision E (January 2007)
This revision includes updates to the packaging diagrams.
TABLE B-1:
DEVICE DIFFERENCES
Features PIC18F1220 4096 2048 15 Ports A, B 1 7 input channels 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN PIC18F1320 8192 4096 15 Ports A, B 1 7 input channels 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN
Program Memory (Bytes) Program Memory (Instructions) Interrupt Sources I/O Ports Enhanced Capture/Compare/PWM Modules 10-bit Analog-to-Digital Module Packages
(c) 2007 Microchip Technology Inc.
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PIC18F1220/1320
APPENDIX C: CONVERSION CONSIDERATIONS APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES
This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable
This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to an enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available
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PIC18F1220/1320
APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES
A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, "Migrating Designs from PIC16C74A/74B to PIC18C442". The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. This Application Note is available as Literature Number DS00716.
A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, "PIC17CXXX to PIC18CXXX Migration". This Application Note is available as Literature Number DS00726.
(c) 2007 Microchip Technology Inc.
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NOTES:
DS39605F-page 294
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INDEX
A
A/D ................................................................................... 155 A/D Converter Interrupt, Configuring ....................... 159 Acquisition Requirements ........................................ 160 ADCON0 Register .................................................... 155 ADCON1 Register .................................................... 155 ADCON2 Register .................................................... 155 ADRESH Register .................................................... 155 ADRESH/ADRESL Registers .................................. 158 ADRESL Register .................................................... 155 Analog Port Pins, Configuring .................................. 162 Associated Registers ............................................... 164 Configuring the Module ............................................ 159 Conversion Clock (Tad) ........................................... 161 Conversion Requirements ....................................... 265 Conversion Status (GO/DONE Bit) .......................... 158 Conversions ............................................................. 163 Converter Characteristics ........................................ 264 Operation in Low-Power Modes ............................... 162 Selecting, Configuring Automatic Acquisition Time ............................................... 161 Special Event Trigger (CCP) .................................... 117 Special Event Trigger (CCP1) .................................. 164 Use of the CCP1 Trigger .......................................... 164 Vref+ and Vref- References ..................................... 160 Absolute Maximum Ratings ............................................. 237 AC (Timing) Characteristics ............................................. 255 Conditions ................................................................ 256 Load Conditions for Device Timing Specifications ....................................... 256 Parameter Symbology ............................................. 255 Temperature and Voltage Specifications ................. 256 ADCON0 Register ............................................................ 155 GO/DONE Bit ........................................................... 158 ADCON1 Register ............................................................ 155 ADCON2 Register ............................................................ 155 ADDLW ............................................................................ 197 ADDWF ............................................................................ 197 ADDWFC ......................................................................... 198 ADRESH Register ............................................................ 155 ADRESH/ADRESL Registers ........................................... 158 ADRESL Register ............................................................ 155 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 198 ANDWF ............................................................................ 199 Assembler MPASM Assembler .................................................. 234 Auto-Wake-up on Sync Break Character ......................... 145 Generic I/O Port Operation ........................................ 87 Low-Voltage Detect (LVD) ....................................... 166 Low-Voltage Detect (LVD) with External Input ........ 166 MCLR/VPP/RA5 Pin ................................................... 89 On-Chip Reset Circuit ................................................ 33 OSC1/CLKI/RA7 Pin .................................................. 88 OSC2/CLKO/RA6 Pin ................................................ 88 PIC18F1220/1320 ....................................................... 7 PLL ............................................................................ 12 RA3:RA0 Pins ............................................................ 88 RA4/T0CKI Pin .......................................................... 88 RB0/AN4/INT0 Pin ..................................................... 90 RB1/AN5/TX/CK/INT1 Pin ......................................... 91 RB2/P1B/INT2 Pin ..................................................... 92 RB3/CCP1/P1A Pin ................................................... 93 RB4/AN6/RX/DT/KBI0 Pin ......................................... 94 RB5/PGM/KBI1 Pin .................................................... 95 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 Pin .................. 96 RB7/PGD/T1OSI/P1D/KBI3 Pin ................................. 97 Reads from Flash Program Memory .......................... 61 System Clock ............................................................. 16 Table Read Operation ............................................... 57 Table Write Operation ................................................ 58 Table Writes to Flash Program Memory .................... 63 Timer0 in 16-Bit Mode ............................................. 100 Timer0 in 8-Bit Mode ............................................... 100 Timer1 ..................................................................... 104 Timer1 (16-Bit Read/Write Mode) ............................ 104 Timer2 ..................................................................... 110 Timer3 ..................................................................... 112 Timer3 (16-bit Read/Write Mode) ............................ 112 WDT ........................................................................ 180 BN .................................................................................... 200 BNC ................................................................................. 201 BNN ................................................................................. 201 BNOV ............................................................................... 202 BNZ .................................................................................. 202 BOR. See Brown-out Reset. BOV ................................................................................. 205 BRA ................................................................................. 203 Break Character (12-bit) Transmit and Receive .............. 146 Brown-out Reset (BOR) ..............................................34, 171 BSF .................................................................................. 203 BTFSC ............................................................................. 204 BTFSS ............................................................................. 204 BTG ................................................................................. 205 BZ .................................................................................... 206
C
C Compilers MPLAB C18 ............................................................. 234 MPLAB C30 ............................................................. 234 CALL ................................................................................ 206 Capture (CCP Module) .................................................... 116 CCP Pin Configuration ............................................. 116 CCPR1H:CCPR1L Registers ................................... 116 Software Interrupt .................................................... 116 Timer1/Timer3 Mode Selection ................................ 116 Capture, Compare, Timer1 and Timer3 Associated Registers ............................................... 118
B
BC .................................................................................... 199 BCF .................................................................................. 200 Block Diagrams A/D ........................................................................... 158 Analog Input Model .................................................. 159 Capture Mode Operation ......................................... 117 Compare Mode Operation ....................................... 118 Enhanced PWM ....................................................... 120 EUSART Receive .................................................... 143 EUSART Transmit ................................................... 141 Fail-Safe Clock Monitor ............................................ 182
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Capture/Compare/PWM (CCP) Capture Mode. See Capture. CCP1 ........................................................................ 116 CCPR1H Register ............................................ 116 CCPR1L Register ............................................ 116 Compare Mode. See Compare. Timer Resources ...................................................... 116 Clock Sources .................................................................... 15 Selection Using OSCCON Register ........................... 16 Clocking Scheme ............................................................... 45 CLRF ................................................................................ 207 CLRWDT .......................................................................... 207 Code Examples 16 x 16 Signed Multiply Routine ................................. 72 16 x 16 Unsigned Multiply Routine ............................. 72 8 x 8 Signed Multiply Routine ..................................... 71 8 x 8 Unsigned Multiply Routine ................................. 71 Changing Between Capture Prescalers ................... 117 Computed GOTO Using an Offset Value ................... 47 Data EEPROM Read ................................................. 69 Data EEPROM Refresh Routine ................................ 70 Data EEPROM Write .................................................. 69 Erasing a Flash Program Memory Row ..................... 62 Fast Register Stack .................................................... 44 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................ 53 Implementing a Real-Time Clock Using a Timer1 Interrupt Service .................................. 107 Initializing PORTA ...................................................... 87 Initializing PORTB ...................................................... 90 Reading a Flash Program Memory Word ................... 61 Saving Status, WREG and BSR Registers in RAM ....................................... 85 Writing to Flash Program Memory ....................... 64-65 Code Protection ............................................................... 171 COMF ............................................................................... 208 Compare (CCP Module) ................................................... 117 CCP Pin Configuration ............................................. 117 CCPR1 Register ....................................................... 117 Software Interrupt ..................................................... 117 Special Event Trigger ....................................... 113, 117 Timer1/Timer3 Mode Selection ................................ 117 Compare (CCP1 Module) Special Event Trigger ............................................... 164 Computed GOTO ............................................................... 47 Configuration Bits ............................................................. 171 Context Saving During Interrupts ....................................... 85 Conversion Considerations .............................................. 292 CPFSEQ .......................................................................... 208 CPFSGT ........................................................................... 209 CPFSLT ........................................................................... 209 Customer Change Notification Service ............................ 302 Customer Notification Service .......................................... 302 Customer Support ............................................................ 302 Data Memory ..................................................................... 47 General Purpose Registers ....................................... 47 Map for PIC18F1220/1320 Devices ........................... 48 Special Function Registers ........................................ 49 DAW ................................................................................ 210 DC and AC Characteristics Graphs and Tables .................................................. 267 DC Characteristics ........................................................... 250 Power-Down and Supply Current ............................ 241 Supply Voltage ......................................................... 240 DCFSNZ .......................................................................... 211 DECF ............................................................................... 210 DECFSZ .......................................................................... 211 Details on Individual Family Members ................................. 6 Development Support ...................................................... 233 Device Differences ........................................................... 291 Direct Addressing ............................................................... 54
E
Effects of Power Managed Modes on Various Clock Sources .............................................. 18 Electrical Characteristics .................................................. 237 Enhanced Capture/Compare/PWM (ECCP) .................... 115 Outputs .................................................................... 116 PWM Mode. See PWM (ECCP Module). Enhanced PWM Mode. See PWM (ECCP Module). ........ 119 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................. 131 Equations 16 x 16 Signed Multiplication Algorithm ..................... 72 16 x 16 Unsigned Multiplication Algorithm ................. 72 A/D Minimum Charging Time ................................... 160 Acquisition Time ...................................................... 160 Errata ................................................................................... 4 EUSART Asynchronous Mode ................................................ 140 12-bit Break Transmit and Receive ................. 146 Associated Registers, Receive ........................ 144 Associated Registers, Transmit ....................... 142 Auto-Wake-up on Sync Break ......................... 145 Receiver .......................................................... 143 Setting up 9-bit Mode with Address Detect ........................................ 143 Transmitter ....................................................... 140 Baud Rate Generator (BRG) ................................... 135 Associated Registers ....................................... 136 Auto-Baud Rate Detect .................................... 139 Baud Rate Error, Calculating ........................... 135 Baud Rates, Asynchronous Modes ................. 136 High Baud Rate Select (BRGH Bit) ................. 135 Power Managed Mode Operation .................... 135 Sampling .......................................................... 135 Serial Port Enable (SPEN Bit) ................................. 131 Synchronous Master Mode ...................................... 148 Associated Registers, Reception ..................... 151 Associated Registers, Transmit ....................... 149 Reception ........................................................ 150 Transmission ................................................... 148 Synchronous Slave Mode ........................................ 152 Associated Registers, Receive ........................ 153 Associated Registers, Transmit ....................... 152 Reception ........................................................ 153 Transmission ................................................... 152
D
Data EEPROM Memory ..................................................... 67 Associated Registers ................................................. 70 EEADR Register ........................................................ 67 EECON1 Register ...................................................... 67 EECON2 Register ...................................................... 67 Operation During Code-Protect .................................. 70 Protection Against Spurious Write ............................. 69 Reading ...................................................................... 69 Using .......................................................................... 70 Write Verify ................................................................. 69 Writing ........................................................................ 69
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F
Fail-Safe Clock Monitor .................................................... 171 Exiting Operation ..................................................... 183 Interrupts in Power Managed Modes ....................... 183 POR or Wake from Sleep ........................................ 184 WDT During Oscillator Failure ................................. 182 Fail-Safe Clock Monitor (FSCM) ...................................... 182 Fast Register Stack ............................................................ 44 Firmware Instructions ....................................................... 191 Flash Program Memory ...................................................... 57 Associated Registers ................................................. 65 Control Registers ....................................................... 58 Erase Sequence ........................................................ 62 Erasing ....................................................................... 62 Operation During Code-Protect ................................. 65 Reading ...................................................................... 61 Table Latch ................................................................ 60 Table Pointer .............................................................. 60 Boundaries Based on Operation ........................ 60 Table Pointer Boundaries .......................................... 60 Table Reads and Table Writes .................................. 57 Write Sequence ......................................................... 63 Writing to .................................................................... 63 Unexpected Termination .................................... 65 Write Verify ........................................................ 65 BRA ......................................................................... 203 BSF .......................................................................... 203 BTFSC ..................................................................... 204 BTFSS ..................................................................... 204 BTG ......................................................................... 205 BZ ............................................................................ 206 CALL ........................................................................ 206 CLRF ....................................................................... 207 CLRWDT ................................................................. 207 COMF ...................................................................... 208 CPFSEQ .................................................................. 208 CPFSGT .................................................................. 209 CPFSLT ................................................................... 209 DAW ........................................................................ 210 DCFSNZ .................................................................. 211 DECF ....................................................................... 210 DECFSZ .................................................................. 211 General Format ........................................................ 193 GOTO ...................................................................... 212 INCF ........................................................................ 212 INCFSZ .................................................................... 213 INFSNZ .................................................................... 213 IORLW ..................................................................... 214 IORWF ..................................................................... 214 LFSR ....................................................................... 215 MOVF ...................................................................... 215 MOVFF .................................................................... 216 MOVLB .................................................................... 216 MOVLW ................................................................... 217 MOVWF ................................................................... 217 MULLW .................................................................... 218 MULWF .................................................................... 218 NEGF ....................................................................... 219 NOP ......................................................................... 219 POP ......................................................................... 220 PUSH ....................................................................... 220 RCALL ..................................................................... 221 RESET ..................................................................... 221 RETFIE .................................................................... 222 RETLW .................................................................... 222 RETURN .................................................................. 223 RLCF ....................................................................... 223 RLNCF ..................................................................... 224 RRCF ....................................................................... 224 RRNCF .................................................................... 225 SETF ....................................................................... 225 SLEEP ..................................................................... 226 SUBFWB ................................................................. 226 SUBLW .................................................................... 227 SUBWF .................................................................... 227 SUBWFB ................................................................. 228 SWAPF .................................................................... 228 TBLRD ..................................................................... 229 TBLWT .................................................................... 230 TSTFSZ ................................................................... 231 XORLW ................................................................... 231 XORWF ................................................................... 232 Summary Table ....................................................... 194 INTCON Register RBIF Bit ..................................................................... 90 INTCON Registers ............................................................. 75
G
GOTO ............................................................................... 212
H
Hardware Multiplier ............................................................ 71 Introduction ................................................................ 71 Operation ................................................................... 71 Performance Comparison .......................................... 71
I
I/O Ports ............................................................................. 87 ID Locations ............................................................. 171, 188 INCF ................................................................................. 212 INCFSZ ............................................................................ 213 In-Circuit Debugger .......................................................... 188 In-Circuit Serial Programming (ICSP) ...................... 171, 188 Indirect Addressing ............................................................ 54 INDF and FSR Registers ........................................... 53 Operation ................................................................... 53 Indirect Addressing Operation ............................................ 54 Indirect File Operand .......................................................... 47 INFSNZ ............................................................................ 213 Initialization Conditions for All Registers ...................... 36-38 Instruction Cycle ................................................................. 45 Instruction Flow/Pipelining ................................................. 45 Instruction Set .................................................................. 191 ADDLW .................................................................... 197 ADDWF .................................................................... 197 ADDWFC ................................................................. 198 ANDLW .................................................................... 198 ANDWF .................................................................... 199 BC ............................................................................ 199 BCF .......................................................................... 200 BN ............................................................................ 200 BNC ......................................................................... 201 BNN ......................................................................... 201 BNOV ....................................................................... 202 BNZ .......................................................................... 202 BOV ......................................................................... 205
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Internal Oscillator Block ..................................................... 14 Adjustment ................................................................. 14 INTIO Modes .............................................................. 14 INTRC Output Frequency .......................................... 14 OSCTUNE Register ................................................... 14 Internal RC Oscillator Use with WDT .......................................................... 180 Internet Address ............................................................... 302 Interrupt Sources .............................................................. 171 A/D Conversion Complete ........................................ 159 Capture Complete (CCP) ......................................... 116 Compare Complete (CCP) ....................................... 117 Interrupt-on-Change (RB7:RB4) ................................ 90 INTn Pin ..................................................................... 85 PORTB, Interrupt-on-Change .................................... 85 TMR0 ......................................................................... 85 TMR0 Overflow ........................................................ 101 TMR1 Overflow ........................................................ 103 TMR2 to PR2 Match ................................................. 110 TMR2 to PR2 Match (PWM) ............................ 109, 119 TMR3 Overflow ................................................ 111, 113 Interrupts ............................................................................ 73 Enable Bits (CCP1IE Bit) .................................................... 116 Flag Bits CCP1 Flag (CCP1IF Bit) .................................. 116 CCP1IF Flag (CCP1IF Bit) ............................... 117 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ........................................... 90 Logic ........................................................................... 74 INTOSC Frequency Drift .................................................... 30 IORLW ............................................................................. 214 IORWF ............................................................................. 214 IPR Registers ..................................................................... 82 MPLAB PM3 Device Programmer ................................... 235 MPLAB REAL ICE In-Circuit Emulator System ................ 235 MPLINK Object Linker/MPLIB Object Librarian ............... 234 MULLW ............................................................................ 218 MULWF ............................................................................ 218
N
NEGF ............................................................................... 219 New Core Features Multiple Oscillator Options and Features ..................... 5 nanoWatt Technology .................................................. 5 NOP ................................................................................. 219
O
Opcode Field Descriptions ............................................... 192 OPTION_REG Register PSA Bit .................................................................... 101 T0CS Bit .................................................................. 101 T0PS2:T0PS0 Bits ................................................... 101 T0SE Bit ................................................................... 101 Oscillator Configuration ...................................................... 11 Crystal/Ceramic Resonator ........................................ 11 EC .............................................................................. 11 ECIO .......................................................................... 11 External Clock Input ................................................... 13 HS .............................................................................. 11 HSPLL ..................................................................11, 12 INTIO1 ....................................................................... 11 INTIO2 ....................................................................... 11 LP .............................................................................. 11 RC .........................................................................11, 13 RCIO .......................................................................... 11 XT .............................................................................. 11 Oscillator Selection .......................................................... 171 Oscillator Start-up Timer (OST) ............................18, 34, 171 Oscillator Switching ............................................................ 15 Oscillator Transitions ......................................................... 18 Oscillator, Timer1 ......................................................103, 113 Oscillator, Timer3 ............................................................. 111 Other Special Features ........................................................ 5
L
LFSR ................................................................................ 215 Low-Voltage Detect .......................................................... 165 Characteristics ......................................................... 253 Effects of a Reset ..................................................... 169 Operation ................................................................. 168 Current Consumption ....................................... 169 Reference Voltage Set Point ............................ 169 Operation During Sleep ............................................ 169 LVD. See Low-Voltage Detect. ........................................ 165
P
Packaging ........................................................................ 285 Details ...................................................................... 286 Marking Information ................................................. 285 PICSTART Plus Development Programmer .................... 236 PIE Registers ..................................................................... 80 Pin Functions MCLR/Vpp/RA5 ........................................................... 8 OSC1/CLKI/RA7 .......................................................... 8 OSC2/CLKO/RA6 ........................................................ 8 RA0/AN0 ...................................................................... 8 RA1/AN1/LVDIN .......................................................... 8 RA2/AN2/Vref- ............................................................. 8 RA3/AN3/VREF+ ........................................................... 8 RA4/T0CKI ................................................................... 8 RB0/AN4/INT0 ............................................................. 9 RB1/AN5/TX/CK/INT1 ................................................. 9 RB2/P1B/INT2 ............................................................. 9 RB3/CCP1/P1A ........................................................... 9 RB4/AN6/RX/DT/KBI0 ................................................. 9 RB5/PGM/KBI1 ............................................................ 9 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 .......................... 9 RB7/PGD/T1OSI/P1D/KBI3 ......................................... 9 Vdd .............................................................................. 9 Vss ............................................................................... 9
M
Memory Organization ......................................................... 41 Data Memory .............................................................. 47 Program Memory ....................................................... 41 Memory Programming Requirements .............................. 252 Microchip Internet Web Site ............................................. 302 Migration from Baseline to Enhanced Devices ................ 292 Migration from High-End to Enhanced Devices ............... 293 Migration from Mid-Range to Enhanced Devices ............. 293 MOVF ............................................................................... 215 MOVFF ............................................................................. 216 MOVLB ............................................................................. 216 MOVLW ............................................................................ 217 MOVWF ........................................................................... 217 MPLAB ASM30 Assembler, Linker, Librarian .................. 234 MPLAB ICD 2 In-Circuit Debugger ................................... 235 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................... 235 MPLAB Integrated Development Environment Software .............................................. 233
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Pinout I/O Descriptions PIC18F1220/1320 ........................................................ 8 PIR Registers ..................................................................... 78 PLL Lock Time-out ............................................................. 34 Pointer, FSR ....................................................................... 53 POP .................................................................................. 220 POR. See Power-on Reset. PORTA Associated Registers ................................................. 89 Functions ................................................................... 89 LATA Register ............................................................ 87 PORTA Register ........................................................ 87 TRISA Register .......................................................... 87 PORTB Associated Registers ................................................. 98 Functions ................................................................... 98 LATB Register ............................................................ 90 PORTB Register ........................................................ 90 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........................................................... 90 TRISB Register .......................................................... 90 Postscaler Timer2 ...................................................................... 109 WDT Assignment (PSA Bit) ...................................... 101 Rate Select (T0PS2:T0PS0 Bits) ..................... 101 Power Managed Modes ..................................................... 19 Comparison between Run and Idle Modes ................ 20 Entering ...................................................................... 20 Idle Modes ................................................................. 21 Multiple Sleep Commands ......................................... 20 Run Modes ................................................................. 26 Selecting .................................................................... 19 Sleep Mode ................................................................ 21 Summary (table) ........................................................ 19 Wake from .................................................................. 28 Power-on Reset (POR) .............................................. 34, 171 Power-up Delays ................................................................ 18 Power-up Timer (PWRT) .......................................18, 34, 171 Prescaler Capture .................................................................... 117 Timer0 ...................................................................... 101 Assignment (PSA Bit) ...................................... 101 Rate Select (T0PS2:T0PS0 Bits) ..................... 101 Timer2 ...................................................................... 119 Product Identification System ........................................... 304 Program Counter PCL Register .............................................................. 44 PCLATH Register ...................................................... 44 PCLATU Register ...................................................... 44 Program Memory Instructions in ............................................................. 46 Interrupt Vector .......................................................... 41 Map and Stack for PIC18F1220 ................................. 41 Map and Stack for PIC18F1320 ................................. 41 Reset Vector .............................................................. 41 Program Verification and Code Protection ....................... 185 Associated Registers ............................................... 185 Configuration Register ............................................. 188 Data EEPROM ......................................................... 188 Program Memory ..................................................... 186 Programming, Device Instructions ................................... 191 PUSH ............................................................................... 220 PUSH and POP Instructions .............................................. 43 PWM (CCP Module) CCPR1H:CCPR1L Registers ................................... 119 Duty Cycle ............................................................... 119 Example Frequencies/Resolutions .......................... 119 Period ...................................................................... 119 TMR2 to PR2 Match .........................................109, 119 PWM (ECCP Module) ...................................................... 119 Associated Registers ............................................... 130 Direction Change in Full-Bridge Output Mode ......... 124 Effects of a Reset .................................................... 129 Enhanced PWM Auto-Shutdown ............................. 126 Full-Bridge Application Example .............................. 124 Full-Bridge PWM Output (Active-High) Diagram ..... 123 Half-Bridge Output (Active-High) Diagram ............... 122 Half-Bridge Output Mode Applications Example ...... 122 Operation in Low-Power Modes .............................. 129 Output Configurations .............................................. 119 Output Relationships (Active-High) .......................... 120 Output Relationships (Active-Low) .......................... 121 Programmable Dead-Band Delay ............................ 126 PWM Direction Change (Active-High) Diagram ....... 125 PWM Direction Change at Near 100% Duty Cycle (Active-High) Diagram ......... 125 Setup for PWM Operation ........................................ 129 Start-up Considerations ........................................... 128
Q
Q Clock ............................................................................ 119
R
RAM. See Data Memory. RCALL ............................................................................. 221 RCIO Oscillator .................................................................. 13 RCON Register Bit Status During Initialization .................................... 35 RCSTA Register SPEN Bit .................................................................. 131 Reader Response ............................................................ 303 Register File ....................................................................... 47 Register File Summary .................................................50-51 Registers ADCON0 (A/D Control 0) ......................................... 155 ADCON1 (A/D Control 1) ......................................... 156 ADCON2 (A/D Control 2) ......................................... 157 BAUDCTL (Baud Rate Control) ............................... 134 CCP1CON (Enhanced CCP1 Control) .................... 115 CONFIG1H (Configuration 1 High) .......................... 172 CONFIG2H (Configuration 2 High) .......................... 174 CONFIG2L (Configuration 2 Low) ........................... 173 CONFIG3H (Configuration 3 High) .......................... 175 CONFIG4L (Configuration 4 Low) ........................... 175 CONFIG5H (Configuration 5 High) .......................... 176 CONFIG5L (Configuration 5 Low) ........................... 176 CONFIG6H (Configuration 6 High) .......................... 177 CONFIG6L (Configuration 6 Low) ........................... 177 CONFIG7H (Configuration 7 High) .......................... 178 CONFIG7L (Configuration 7 Low) ........................... 178 DEVID1 (Device ID 1) .............................................. 179 DEVID2 (Device ID 2) .............................................. 179 ECCPAS (ECCP Auto-Shutdown Control) .............. 127 EECON1 (Data EEPROM Control 1) ....................59, 68 INTCON (Interrupt Control) ........................................ 75 INTCON2 (Interrupt Control 2) ................................... 76 INTCON3 (Interrupt Control 3) ................................... 77 IPR1 (Peripheral Interrupt Priority 1) ......................... 82 IPR2 (Peripheral Interrupt Priority 2) ......................... 83 LVDCON (LVD Control) ........................................... 167 OSCCON (Oscillator Control) .................................... 17
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OSCTUNE (Oscillator Tuning) ................................... 15 PIE1 (Peripheral Interrupt Enable 1) .......................... 80 PIE2 (Peripheral Interrupt Enable 2) .......................... 81 PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 78 PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 79 PWM1CON (PWM Configuration) ............................ 126 RCON (Reset Control) ......................................... 56, 84 RCSTA (Receive Status and Control) ...................... 133 Status ......................................................................... 55 STKPTR (Stack Pointer) ............................................ 43 T0CON (Timer0 Control) ............................................ 99 T1CON (Timer 1 Control) ......................................... 103 T2CON (Timer 2 Control) ......................................... 109 T3CON (Timer3 Control) .......................................... 111 TXSTA (Transmit Status and Control) ..................... 132 WDTCON (Watchdog Timer Control) ....................... 180 RESET ............................................................................. 221 Reset .......................................................................... 33, 171 RETFIE ............................................................................ 222 RETLW ............................................................................. 222 RETURN .......................................................................... 223 Return Address Stack ........................................................ 42 and Associated Registers .......................................... 42 Return Stack Pointer (STKPTR) ........................................ 42 Revision History ............................................................... 291 RLCF ................................................................................ 223 RLNCF ............................................................................. 224 RRCF ............................................................................... 224 RRNCF ............................................................................. 225 Timer1 .............................................................................. 103 16-Bit Read/Write Mode .......................................... 106 Associated Registers ............................................... 108 Interrupt ................................................................... 106 Operation ................................................................. 104 Oscillator ...........................................................103, 105 Layout Considerations ..................................... 106 Overflow Interrupt .................................................... 103 Resetting, Using a Special Event Trigger Output (CCP) ................................................... 106 Special Event Trigger (CCP) ................................... 117 TMR1H Register ...................................................... 103 TMR1L Register ....................................................... 103 Use as a Real-Time Clock ....................................... 107 Timer2 .............................................................................. 109 Associated Registers ............................................... 110 Operation ................................................................. 109 Output ...................................................................... 110 Postscaler. See Postscaler, Timer2. PR2 Register ....................................................109, 119 Prescaler. See Prescaler, Timer2. TMR2 Register ......................................................... 109 TMR2 to PR2 Match Interrupt ...................109, 110, 119 Timer3 .............................................................................. 111 Associated Registers ............................................... 113 Operation ................................................................. 112 Oscillator ...........................................................111, 113 Overflow Interrupt .............................................111, 113 Special Event Trigger (CCP) ................................... 113 TMR3H Register ...................................................... 111 TMR3L Register ....................................................... 111 Timing Diagrams A/D Conversion ........................................................ 265 Asynchronous Reception ......................................... 144 Asynchronous Transmission .................................... 141 Asynchronous Transmission (Back to Back) ........... 142 Auto-Wake-up Bit (WUE) During Normal Operation ............................................ 145 Auto-Wake-up Bit (WUE) During Sleep ................... 145 Brown-out Reset (BOR) ........................................... 260 Capture/Compare/PWM (All CCP Modules) ............ 262 CLKO and I/O .......................................................... 259 Clock/Instruction Cycle .............................................. 45 EUSART Synchronous Receive (Master/Slave) ................................................. 264 EUSART SynchronousTransmission (Master/Slave) ................................................. 263 External Clock (All Modes Except PLL) ................... 257 Fail-Safe Clock Monitor ........................................... 183 Low-Voltage Detect ................................................. 168 Low-Voltage Detect Characteristics ......................... 253 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 128 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 128 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ..... 260 Send Break Character Sequence ............................ 147 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 40 Synchronous Reception (Master Mode, SREN) ..................................... 150 Synchronous Transmission ..................................... 148 Synchronous Transmission (Through TXEN) .......... 149
S
SETF ................................................................................ 225 SLEEP .............................................................................. 226 Sleep OSC1 and OSC2 Pin States ...................................... 18 Software Simulator (MPLAB SIM) .................................... 234 Special Event Trigger. See Compare Special Features of the CPU ............................................ 171 Configuration Registers .................................... 172-178 Special Function Registers ................................................ 49 Map ............................................................................ 49 Stack Full/Underflow Resets .............................................. 43 SUBFWB .......................................................................... 226 SUBLW ............................................................................ 227 SUBWF ............................................................................ 227 SUBWFB .......................................................................... 228 SWAPF ............................................................................ 228
T
TABLAT Register ............................................................... 60 Table Pointer Operations (table) ........................................ 60 TBLPTR Register ............................................................... 60 TBLRD ............................................................................. 229 TBLWT ............................................................................. 230 Time-out Sequence ............................................................ 34 Timer0 ................................................................................ 99 16-Bit Mode Timer Reads and Writes ...................... 101 Associated Registers ............................................... 101 Clock Source Edge Select (T0SE Bit) ...................... 101 Clock Source Select (T0CS Bit) ............................... 101 Operation ................................................................. 101 Overflow Interrupt ..................................................... 101 Prescaler. See Prescaler, Timer0. Switching Prescaler Assignment .............................. 101
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Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ........................................... 40 Time-out Sequence on Power-up (MCLR Not Tied to Vdd), Case 1 ....................... 39 Time-out Sequence on Power-up (MCLR Not Tied to Vdd), Case 2 ....................... 39 Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise pwrt) ................... 39 Timer0 and Timer1 External Clock .......................... 261 Transition for Entry to SEC_IDLE Mode .................... 24 Transition for Entry to SEC_RUN Mode .................... 26 Transition for Entry to Sleep Mode ............................ 22 Transition for Two-Speed Start-up (INTOSC to HSPLL) ......................................... 181 Transition for Wake from PRI_IDLE Mode ................. 23 Transition for Wake from RC_RUN Mode (RC_RUN to PRI_RUN) ..................................... 25 Transition for Wake from SEC_RUN Mode (HSPLL) ............................................................. 24 Transition for Wake from Sleep (HSPLL) ................... 22 Transition to PRI_IDLE Mode .................................... 23 Transition to RC_IDLE Mode ..................................... 25 Transition to RC_RUN Mode ..................................... 27 Timing Diagrams and Specifications ................................ 257 Capture/Compare/PWM Requirements (All CCP Modules) ........................................... 263 CLKO and I/O Requirements ................................... 259 EUSART Synchronous Receive Requirements ....... 264 EUSART Synchronous Transmission Requirements ............................ 263 External Clock Requirements .................................. 257 Internal RC Accuracy ............................................... 258 PLL Clock, HS/HSPLL Mode (VDD = 4.2V to 5.5V) ........................................ 258 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ....................... 261 Timer0 and Timer1 External Clock Requirements ................................................... 262 Top-of-Stack Access .......................................................... 42 TSTFSZ ........................................................................... 231 Two-Speed Start-up ..................................................171, 181 Two-Word Instructions ....................................................... 46 Example Cases .......................................................... 46 TXSTA Register BRGH Bit ................................................................. 135
W
Watchdog Timer (WDT) ............................................171, 180 Associated Registers ............................................... 181 Control Register ....................................................... 180 During Oscillator Failure .......................................... 182 Programming Considerations .................................. 180 WWW Address ................................................................ 302 WWW, On-Line Support ...................................................... 4
X
XORLW ............................................................................ 231 XORWF ........................................................................... 232
(c) 2007 Microchip Technology Inc.
DS39605F-page 301
PIC18F1220/1320
NOTES:
DS39605F-page 302
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2007 Microchip Technology Inc.
DS39605F-page 303
PIC18F1220/1320
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC18F1220/1320 Questions: 1. What are the best features of this document? Y N Literature Number: DS39605F FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39605F-page 304
(c) 2007 Microchip Technology Inc.
PIC18F1220/1320
PIC18F1220/1320 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. Device
-
X Temperature Range
/XX Package
XXX Pattern
Examples: a) PIC18LF1320-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF1220-I/SO = Industrial temp., SOIC package, Extended VDD limits.
Device
PIC18F1220/1320(1), PIC18F1220/1320T(2); VDD range 4.2V to 5.5V PIC18LF1220/1320(1), PIC18LF1220/1320T(2); VDD range 2.5V to 5.5V
b)
Temperature Range Package
I E
= =
-40C to +85C (Industrial) -40C to +125C (Extended) SS = SSOP ML = QFN
Note 1: 2:
F = Standard Voltage range LF = Wide Voltage Range T = in tape and reel - SOIC package only
SO = SOIC P = PDIP
Pattern
QTP, SQTP, Code or Special Requirements (blank otherwise)
(c) 2007 Microchip Technology Inc.
DS39605F-page 305
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
12/08/06
DS39605F-page 306
(c) 2007 Microchip Technology Inc.

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